DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, per page 11, filed January 28, 2026, with respect to the title have been fully considered and are persuasive. The objection of November 7, 2025 has been withdrawn.
Applicant's arguments filed January 28, 2026 have been fully considered but they are not persuasive.
Regarding Claim 1, applicant amends the claim to now read the limitation “a separation pattern disposed between a first sub-plug and a second sub-plug within the main plug, wherein the first sub-plug and the second sub-plug are spaced apart from each other” and asserts that Baenninger’s annotated Fig. 1C does not disclose two distinct sub-plugs physically separated by the separation pattern. However, the amendment only requires that the first sub-plug and second sub-plug be spaced apart by the separation pattern and does not explicitly require the sub-plugs to be physically spaced apart. For this reason an updated rejection is presented below to read the new limitations.
Regarding Claim 22, applicant amends the claim to now read the limitation “a separation pattern disposed between a first sub-plug and a second sub-plug within the main plug, wherein the first sub-plug and the second sub-plug are spaced apart from each other” and asserts that Baenninger’s annotated Fig. 1C does not disclose two distinct sub-plugs physically separated by the separation pattern. However, the amendment only requires that the first sub-plug and second sub-plug be spaced apart by the separation pattern and does not explicitly require the sub-plugs to be physically spaced apart. For this reason an updated rejection is presented below to read the new limitations.
Status of the Claims
Claim 7 is canceled. Claims 12-21 are withdrawn. Claims 1, 8, and 22 are amended. Claims 1-6, 8-11, and 22-28 are present for examination.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6, 8-9, 22, and 29 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Baenninger (US 2016/0141419). Claim 1, Baenninger discloses (see annotated Fig. 1C below and Fig. 3A) a memory device comprising: a stacked structure (120, stack, Para [0019]) including a drain selection line (34, drain side select gate electrodes, Para [0060]), word lines (3a/3b, source control gate electrodes form word lines, Para [0038]), and a source selection line (33, source side select gate electrodes, Para [0060]) that are sequentially stacked (34, 3a/3b, and 33 are sequentially stacked); a main plug (150, NAND strings, Para [0018]) extending through stacked structure (150 extends through 120); a separation pattern (2, insulating fill material, Para [0018]) disposed between (2 is between 1st and 2nd) a first sub-plug (1st, portions of 150) and a second sub-plug (2nd, portion of 150) within the main plug (1st and 2nd are within 150) , wherein the first sub-plug and the second sub-plug are spaced apart from each other (under broadest reasonable interpretation (BRI) 1st and 2nd are spaced apart from each other by 2 in the annotated Fig. 1C below) ; and a source line (102a/302, source contact/p-well, Para [0054], hereinafter “sline”) stacked over the stacked structure (sline is stacked over 120), and comprising a sub source layer (102a), wherein the sub source layer (102a) protrudes into a central portion of an upper area of the main plug (102a protrudes into a central portion of an upper area of 150).
PNG
media_image1.png
914
904
media_image1.png
Greyscale
Claim 2, Baenninger discloses (see annotated Fig. 1C above and Fig. 3A) the memory device according to claim 1, wherein: the drain selection line (34) is disposed in a lower portion of the stacked structure (34 is disposed in a lower portion of 120), and the source selection line (33) is disposed in an upper portion of the stacked structure (33 is disposed in an upper portion of 120). Claim 3, Baenninger discloses (see annotated Fig. 1C above and Fig. 3A) the memory device according to claim 1, wherein the main plug (150) comprises (150 comprises 1/2/13) a blocking layer (Fig. 3A, 13 includes 7, blocking dielectric, Para [0043]) , a charge trap layer (Fig. 3A, 9, charge storage region, Para [0042]) , a tunnel insulating layer (11, tunnel dielectric, Para [0042]), a channel layer (1, semiconductor channel, Para [0042]), a core pillar (2 function as a core dielectric pillar as well as separation pattern), and a capping layer (103a, doped drain region, Para [0045]) that extend in the vertical direction (all 150 elements extend in vertical direction). Claim 4, Baenninger discloses (see annotated Fig. 1C above and Fig. 3A) the memory device according to claim 3, wherein a bottom surface (bottom surface of 102a) of the sub-source layer (102a) contacts the core pillar of the main plug and the separation pattern (as can be seen in annotated Fig. 1C, the bottom surface of 102a contacts 2 which is both the core pillar and separation pattern). Claim 5, Baenninger discloses (see annotated Fig. 1C above and Fig. 3A) the memory device according to claim 3, wherein a side surface of the sub-source layer (side surface of 102a) contacts an inner surface of the channel layer (Fig. 1C, side surface of 102a contacts and inner surface of 1). Claim 6, Baenninger discloses (see annotated Fig. 1C above and Fig. 3A) the memory device according to claim 3, wherein the blocking layer of the main plug is enclosed by the source line (since 13 is enclosed by 33 in Fig. 1C, so would 7 which is part of 13).
Claim 8, Baenninger discloses (see annotated Fig. 1C above and Fig. 3A) the memory device according to claim 1, wherein the first (1st) and second sub- plugs (2nd) have structures symmetrical to each other with respect to the separation pattern (as can be seen in Fig. 1C above 1st and 2nd are symmetrical to each other with respect to 2). Claim 9, Baenninger discloses (see annotated Fig. 1C above and Fig. 3A) the memory device according to claim 1, wherein the separation pattern (2) is formed of an insulating material (2 is insulating fill material, Para [0018]). Claim 22, Baenninger discloses (annotated Fig. 1C below and Fig. 3A) a memory device comprising: a stacked structure (120, stack, Para [0019]) including a drain selection line (34, drain side select gate electrodes, Para [0060]), word lines (3a/3b, source control gate electrodes form word lines, Para [0038]), and a source selection line (33, source side select gate electrodes, Para [0060]) that are sequentially stacked (34, 3a/3b, and 33 are sequentially stacked); a main plug (150, NAND strings, Para [0018]) extending through the stacked structure (150 extends through 120), and including a sub- source layer hole (area where 102a fills, hereinafter “subhole”) in a central portion of an upper area of the main plug (subhole is in a central portion of upper area of 150); a separation pattern (2, insulating fill material, Para [0018]) disposed between (2 is between 1st and 2nd) a first sub-plug (1st, portions of 150) and a second sub-plug (2nd, portion of 150) within the main plug (1st and 2nd are within 150) , wherein the first sub-plug and the second sub-plug are spaced apart from each other (under broadest reasonable interpretation (BRI) 1st and 2nd are spaced apart from each other by 2 in the annotated Fig. 1C below) ;
a source line (102a/302, source contact/p-well, Para [0054], hereinafter “sline”) stacked over the stacked structure (sline is stacked over 120), and comprising a sub source layer (102a) which fills the sub-source layer hole (102a fills subhole); and a blocking layer (shown in Fig. 3A as part of 13, 7, blocking dielectric, Para [0043]), a charge trap layer (Fig. 3A, 9, charge storage region, Para [0042]), a tunnel insulating layer (11, tunnel dielectric, Para [0042]), and a channel layer (1, semiconductor channel, Para [0042]) disposed adjacent the sub-source layer hole (1 is disposed adjacent to subhole) and extending in the vertical direction away from the sub-source layer (1 extends in the vertical direction away from 102a), wherein the sub-source layer (102a) protrudes in a direction close to a bottom of the separation pattern (102a protrudes vertically which is a direction close to a bottom of 2) and directly contacts the channel layer (102a directly contacts 1).
PNG
media_image1.png
914
904
media_image1.png
Greyscale
Claim 29, Baenninger discloses (see annotated Fig. 1C above and Fig. 3A) the memory device according to claim 3, wherein: the capping layer (103a) is formed of a conductive material (103a is conductive doped drain region, Para [0028]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 10-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Baenninger (US 2016/0141419) as applied to claim 1 above, and further in view of Sotome (US 2020/0295036). Claim 10, Baenninger discloses the memory device according to claim 1. Baenninger does not explicitly disclose further comprising: an air gap formed in the separation pattern; and a gap-fill layer configured to fill the air gap. However, Sotome discloses (Figs. 11-12) an air gap (Fig. 11, MH, memory hole is considered air gap in the separation pattern 42A, Para [0104])) formed in a separation pattern (42A, core insulation layer, Para [0117]); and a gap-fill layer (Fig. 12, 42B partially fills MH, core insulation layer, Para [0130]) configured to fill the air gap (MH). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the separation pattern with a filled air gap of Sotome to the device of Baenninger as it can help reduce thinning of the semiconductor channel (Sotome, Para [0117]). Claim 11, Baenninger in view of Sotome discloses the memory device according to claim 10, wherein the gap-fill layer (42B of Sotome) is formed of a material identical to that of the separation (42A of Sotome) pattern (42B and 42A of Sotome can both be silicon oxide, Sotome, Para [0077], [0070]).
Allowable Subject Matter
Claims 23-28 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The following is an examiner’s statement of reasons for allowance: the closest prior art of record, Baenninger (US 2016/0141419), Sotome (US 2020/0295036), fail to disclose (by themselves or in combination) the following limitations in combination with the rest of the claim:
Regarding Claim 23 (from which Claims 24-28 depend), a second source layer disposed under the first source layer, wherein a boundary between the first source layer and the second source layer is at a same level as a portion at which the blocking layer, the charge trap layer, the tunnel insulating layer and the channel layer of the main plug contact the first source layer.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUSTAVO G RAMALLO whose telephone number is (571)272-9227. The examiner can normally be reached Monday-Friday 10am - 6pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/G.G.R/Examiner, Art Unit 2812 /William B Partridge/Supervisory Patent Examiner, Art Unit 2812