CTNF 18/175,591 CTNF 88273 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1- are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by U.S. Pat. Pub. No. 20180315667 to Kwon et al. (Kwon) . Regarding Claim 1 , Kwon teaches in Fig. 9 at least, an integrated circuit (IC) structure, comprising: a first stack of nanoribbons 102 over NFET , wherein portions of the nanoribbons of the first stack are channel regions of N-type transistors NFET ; a second stack of nanoribbons 102 over PFET , wherein portions of the nanoribbons of the second stack are channel regions of P-type transistors PFET ; a first gate region over NFET enclosing portions of the nanoribbons of the first stack and comprising an N-type work function (NWF) material 502 between adjacent nanoribbons of the first stack; and a second gate region over PFET enclosing portions of the nanoribbons of the second stack and comprising a P-type work function (PWF) material 501 between adjacent nanoribbons of the second stack, wherein the second gate region includes the PWF material at sidewalls of the nanoribbons of the second stack and further includes the NWF material so that the PWF material is between the sidewalls of the nanoribbons of the second stack and the NWF material (see Fig. 9) . Regarding Claim 2 , Kwon teaches the IC structure according to claim 1, wherein the PWF material between the sidewalls of the nanoribbons of the second stack and the NWF material has one side in contact with the sidewalls of the nanoribbons of the second stack and has another side in contact with the NWF material (see Fig. 9) . Regarding Claim 3 , Kwon teaches the IC structure according to claim 1, wherein, in the first gate region, the PWF material is absent between the adjacent nanoribbons of the first stack (see Fig. 9) . Regarding Claim 4 , Kwon teaches the IC structure according to claim 1, wherein, in the first gate region, the NWF material fills areas between the adjacent nanoribbons of the first stack (see Fig. 9) . Regarding Claim 5 , Kwon teaches the IC structure according to claim 4, wherein the first gate region further includes a gate dielectric material 301Left on the adjacent nanoribbons of the first stack, and wherein the NWF material fills areas between the gate dielectric material on the adjacent nanoribbons of the first stack. Regarding Claim 6 , Kwon teaches the IC structure according to claim 1, wherein, in the second gate region, the PWF material fills areas between the adjacent nanoribbons of the second stack (see Fig. 9) . Regarding Claim 7 , Kwon teaches the IC structure according to claim 6, wherein the second gate region further includes a gate dielectric material 301Right on the adjacent nanoribbons of the second stack, and wherein the PWF material fills areas between the gate dielectric material on the adjacent nanoribbons of the second stack. Regarding Claim 8 , Kwon teaches the IC structure according to claim 1, further comprising a gate fill material 503 , the gate fill material including: a first portion in the first gate region above an uppermost nanoribbon of the first stack, and a second portion in the second gate region above an uppermost nanoribbon of the second stack, wherein the gate fill material is absent between the adjacent nanoribbons of the second stack in the second gate region (see Fig. 9) . Regarding Claim 9 , Kwon teaches the IC structure according to claim 8, wherein the first portion and the second portion are materially continuous portions of the gate fill material in the first gate region and the second gate region (see Fig. 9) . Regarding Claim 10 , Kwon teaches the IC structure according to claim 8, wherein, in the first gate region, sidewalls of the nanoribbons of the first stack are in contact with one side of the NWF material, and another side of the NWF material is in contact with the gate fill material (see Fig. 9) . Regarding Claim 11 , Kwon teaches the IC structure according to claim 1, wherein, in a cross-section of the second stack in the second gate region in a plane substantially perpendicular to a longitudinal axis of one of the nanoribbons of the second stack, a portion of the PWF material below a lowermost nanoribbon of the second stack has a step profile (see Fig. 9) . Regarding Claim 12 , Kwon teaches the IC structure according to claim 1, wherein, in a cross-section of the second stack in the second gate region in a plane substantially perpendicular to a longitudinal axis of one of the nanoribbons of the second stack, a first portion (horizontal portion of 501 extending from stack) of the PWF material below a lowermost nanoribbon of the second stack has a first thickness and a second portion (between horizontal extending portion of 501 and fin 100) of the PWF material below the lowermost nanoribbon of the second stack has a second thickness that is different from the first thickness. Regarding Claim 13 , Kwon teaches an integrated circuit (IC) structure, comprising: a first stack of nanoribbons 102 over NFET ; a second stack of nanoribbons 102 over PFET ; a first gate region over NFET enclosing portions of the nanoribbons of the first stack and comprising an N-type work function (NWF) material 502 between adjacent nanoribbons of the first stack; and a second gate region over PFET enclosing portions of the nanoribbons of the second stack and comprising a P-type work function (PWF) material 501 between adjacent nanoribbons of the second stack, wherein, in the first gate region, the NWF material fills areas between the adjacent nanoribbons of the first stack (see Fig. 9) . Regarding Claim 14 , Kwon teaches the IC structure according to claim 13, wherein the PWF material is absent between the adjacent nanoribbons of the first stack in the first gate region (see Fig. 9) . Regarding Claim 15 , Kwon teaches the IC structure according to claim 14, wherein the first gate region further includes a gate dielectric material 301 on the adjacent nanoribbons of the first stack, and wherein the NWF material fills areas between the gate dielectric material on the adjacent nanoribbons of the first stack (see Fig. 9) . Regarding Claim 16 , Kwon teaches the IC structure according to claim 13, wherein, in the second gate region, the PWF material fills areas between the adjacent nanoribbons of the second stack (see Fig. 9) . Regarding Claim 17 , Kwon teaches the IC structure according to claim 13, wherein, in a cross-section of the second stack in the second gate region in a plane substantially perpendicular to a longitudinal axis of one of the nanoribbons of the second stack, a first portion of the PWF material below a lowermost nanoribbon of the second stack has a first thickness and a second portion of the PWF material below the lowermost nanoribbon of the second stack has a second thickness that is different from the first thickness (see above rejection of claim 12) . Regarding Claim 18 , Kwon teaches in Figs. 1-9 at least, a method of fabricating an integrated circuit (IC) structure, the method comprising: providing a first stack of nanoribbons 102 over NFET and a second stack nanoribbons 102 over PFET ; depositing one or more layers of a P-type work function (PWF) material 501 to partially surround channel regions of the nanoribbons of the first stack and to surround channel regions of the nanoribbons of the second stack (see Fig. 3) ; removing the PWF material surrounding the channel regions of the nanoribbons of the first stack (see Fig. 7) ; and depositing an N-type work function (NWF) material 502 to surround the channel regions of the nanoribbons of the first stack after removing the PWF material surrounding the channel regions of the nanoribbons of the first stack (see Fig. 8) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kwon as applied to Claim 18 above in view of U.S. Pat. Pub. No. 20210202327 to Wang et al. (Wang) . Regarding Claims 19 and 20 , Kwon teaches the method according to claim 18, further but does not explicitly teach: plugging areas between the channel regions of adjacent nanoribbons of the first stack with a sacrificial material prior to depositing the one or more layers of the PWF material to partially surround channel regions of the nanoribbons of the first stack, and removing the sacrificial material prior to depositing the NWF material to surround the channel regions of the nanoribbons of the first stack. However, in analogous art, Wang teaches in Fig. 20A-20H at least, leaving a sacrificial material 210 between a first stack of nanosheets 25 while depositing a WFM 104 on an opposite stack of nanosheets, then removing the sacrificial material to deposit a second WFM on the first stack of nanosheets. It would have been obvious to the person of ordinary skill in the art before the time of filing to include the teaching of Wang to prevent the WFM deposited first from accumulating between the first stack of nanosheets, as taught by Wang. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to EVREN SEVEN whose telephone number is (571)270-5666. The examiner can normally be reached Mon-Fri 8:00- 5:00 Pacific. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at (571) 272-8458. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /EVREN SEVEN/Primary Examiner, Art Unit 2812 Application/Control Number: 18/175,591 Page 2 Art Unit: 2812 Application/Control Number: 18/175,591 Page 3 Art Unit: 2812 Application/Control Number: 18/175,591 Page 4 Art Unit: 2812 Application/Control Number: 18/175,591 Page 5 Art Unit: 2812 Application/Control Number: 18/175,591 Page 6 Art Unit: 2812 Application/Control Number: 18/175,591 Page 7 Art Unit: 2812 Application/Control Number: 18/175,591 Page 8 Art Unit: 2812
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