DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02/10/2026 has been entered.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Response to Arguments
Applicant's arguments filed 02/10/2026 have been fully considered but they are not persuasive.
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Applicant argues Yamada does not explicitly teach or suggest claim 9 as amended including the limitation “the first insulator layer directly contacts the second insulator layer and the first insulator layer.”
However, FIG. 1B of Yamada explicitly teaches the first insulator layer (40) directly contacting the second insulator layer (14) and the third insulator layer (12).
Thus, the previous rejection over Yamada in view of Silverman stands. See below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 9 and 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Yamada (US 20180061697 A1; hereinafter Yamada) in view of Silverman (US 20040151988 A1; hereinafter Silverman).
Regarding claim 9, FIG. 1B of Yamada teaches a semiconductor device (e.g. FIG. 1B) comprising: a substrate (10) having a first upper surface (upper surface of 10 ¶ [0014]); a semiconductor layer (11) provided on the substrate (10 ¶ [0015]); a first insulator layer (40) provided over the semiconductor layer (11) and having a second upper surface (upper surface of 40 ¶ [0014]); a lower electrode (32) provided over the first insulator layer (40 ¶ [0021]); a dielectric layer (22) provided on the lower electrode (32 ¶ [0019], e.g. on a sidewall of 32); an upper electrode (24) provided on the dielectric layer (22 ¶ [0019]); a second insulator layer (14) provided between the first insulator layer (40) and the lower electrode (32) and including silicon (e.g. SiN ¶ [0020]); a third insulator layer (12) provided between the semiconductor layer (11) and the first insulator layer (40) and including silicon (e.g. SiN ¶ [0017]), wherein the second insulator layer (14) directly contacts the third insulator layer (12), wherein a difference between a maximum value and a minimum value of a distance between the first upper surface of the substrate (upper surface of 10) and the second upper surface of the first insulator layer (upper surface of 40, e.g. a difference of 0 nm) is smaller than a thickness of the semiconductor layer (thickness of 11), and wherein the first insulator layer (40) directly contacts the second insulator layer (14) and the third insulator layer (12). The Examiner notes the term “lower” has been interpreted under broadest reasonable interpretation (BRI, MPEP § 2111.01) as meaning “electrically lower.”
Yamada does not teach wherein the first insulator layer is a polyimide layer.
FIGS. 1A-2B of Silverman teach a semiconductor structure comprising: a substrate (100 ¶ [0016]); and a polyimide layer (120) provided on the substrate (100 ¶ [0018]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught by Nakano with the polyimide layer taught by Silverman for the purpose of eliminating/minimizing defects (¶ [0018]) and since it has been held that the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960), and MPEP 2144.07 Art Recognized Suitability for an Intended Purpose.
Regarding claim 11, Yamada as modified teaches the semiconductor device according to claim 9, and FIG. 1B of Yamada further teaches wherein the difference between the maximum value and the minimum value is 100 nm or less (e.g. 0 nm).
Regarding claim 12, Yamada as modified teaches the semiconductor device according to claim 9, and FIG. 1B of Yamada further teaches wherein the difference between the maximum value and the minimum value is 50 nm or less (e.g. 0 nm).
Regarding claim 13, Yamada as modified teaches the semiconductor device according to claim 9, and Yamada further teaches wherein the semiconductor layer (11) is a nitride semiconductor layer (e.g. GaN ¶ [0015]).
Allowable Subject Matter
Claims 10 and 14-16 are allowed.
The following is an examiner’s statement of reasons for allowance:
Claim 10 recites a semiconductor device comprising: a substrate having a first upper surface; a semiconductor layer provided on the substrate, and having a pit penetrating the semiconductor layer; a first insulator layer provided over the semiconductor layer and having a second upper surface; a lower electrode provided over the first insulator layer; a dielectric layer provided on the lower electrode; an upper electrode provided on the dielectric layer; a second insulator layer provided between the first insulator layer and the lower electrode and including silicon; and a third insulator layer provided between the semiconductor layer and the first insulator layer and including silicon, wherein a difference between a maximum value and a minimum value of a distance between the first upper surface of the substrate and the second upper surface of the first insulator layer is smaller than a thickness of the semiconductor layer, above the pit in the semiconductor layer, wherein the first insulator layer is a polyimide layer and is filing the pit of the semiconductor layer, wherein the first insulator layer directly contacts the second insulator layer and the third insulator layer, and wherein the second insulator layer directly contacts the third insulator layer.
FIG. 1B of Yamada teaches a semiconductor device (e.g. FIG. 1B) comprising: a substrate (10) having a first upper surface (upper surface of 10 ¶ [0014]); a semiconductor layer (11) provided on the substrate (10 ¶ [0015]); a first insulator layer (40) provided over the semiconductor layer (11) and having a second upper surface (upper surface of 40 ¶ [0014]); a lower electrode (32) provided over the first insulator layer (40 ¶ [0021]); a dielectric layer (22) provided on the lower electrode (32 ¶ [0019], e.g. on a sidewall of 32); an upper electrode (24) provided on the dielectric layer (22 ¶ [0019]); a second insulator layer (14) provided between the first insulator layer (40) and the lower electrode (32) and including silicon (e.g. SiN ¶ [0020]); a third insulator layer (12) provided between the semiconductor layer (11) and the first insulator layer (40) and including silicon (e.g. SiN ¶ [0017]), wherein the second insulator layer (14) directly contacts the third insulator layer (12), and wherein a difference between a maximum value and a minimum value of a distance between the first upper surface of the substrate (upper surface of 10) and the second upper surface of the first insulator layer (upper surface of 40, e.g. a difference of 0 nm) is smaller than a thickness of the semiconductor layer (thickness of 11).
FIGS. 1A-2B of Silverman teach a semiconductor structure comprising: a substrate (100 ¶ [0016]); and a polyimide layer (120) provided on the substrate (100 ¶ [0018]).
However, the prior art fails to teach or reasonably suggest “wherein the first insulator layer… is filling the pit of the semiconductor layer” together with all the limitations of claim 10 as claimed. Claims 14-16 are allowable insofar as they depend upon and require all the limitations of claim 10.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nora T Nix whose telephone number is (571)270-1972. The examiner can normally be reached Monday - Friday 9:00 am - 5:00 pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571) 272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Nora T. Nix/Assistant Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891