Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 17 are rejected under 35 U.S.C. 103 as being unpatentable over Hwang ( Pub. No. US 20200312862 A1 ), hereinafter Hwang, in view of Kim (Pub. No. 20190319039 A1), hereinafter Kim.
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Regarding Independent Claim 1 ( Currently Amended ), Hwang teaches a semiconductor memory device comprising:
a first chip (Hwang, FIG. 18, the bottom chip including 193 / ML / PL / BL; [0060] protection layer 193; [0059] upper interconnection lines ML; [0043] peripheral line PL; [0026] bit lines BL);
a second chip (Hwang, FIG. 18, C2; the chip bonded above the first chip including GP / 120 / VS / 10S; [0031], second semiconductor chip C2; [0044] gate electrodes GP, insulating layers 120; [0050] vertical structures VS; [0062] second body conductive layer 10S) bonded to the first chip;
a third chip (Hwang, FIG. 18, C1; the chip bonded above the second chip on a side opposite to the first chip including GP / 120 / VS / 10F; [0031], first semiconductor chip C1; [0044] gate electrodes GP, insulating layers 120; [0050] vertical structures VS; [0062] first body conductive layer 10F) bonded to the second chip on a side opposite to the first chip; and
a fourth chip (Hwang, FIG. 18, the top chip including 193 / ML / PL / BL; [0060] protection layer 193; [0059] upper interconnection lines ML; [0043] peripheral line PL; [0026] bit lines BL) bonded to the third chip on a side opposite to the second chip, wherein
the third chip (Hwang, FIG. 18, C1; the chip bonded above the second chip on a side opposite to the first chip including GP / 120 / VS / 10F; [0031], first semiconductor chip C1; [0044] gate electrodes GP, insulating layers 120; [0050] vertical structures VS; [0062] first body conductive layer 10F) includes a first stacked body (Hwang, FIG. 18, stacked body including GP and 120; [0044] electrode structures ST including gate electrodes GP and insulating layers 120) in which a plurality of first conductive layers (Hwang, FIG. 18, gate electrodes GP; [0044] gate electrodes GP) are stacked in a first direction (Hwang, FIG. 18, vertical Z-direction D3) through a first insulating layer (Hwang, FIG. 18, insulating layers 120; [0044] insulating layers 120), a plurality of first semiconductor films (Hwang, FIG. 18, vertical structures VS; [0050] vertical structures VS extending vertically) each extending in the first direction (Hwang, FIG. 18, vertical Z-direction) through the first stacked body (Hwang, FIG. 18, stacked body including GP and 120), and a plurality of first insulating films (Hwang, FIG. 3A, 3B, 139, blocking insulating layer, tunnel insulating layer; [0051] As shown in FIGS. 3A and 3B, each of the vertical structures VS may include a buried insulating layer 139; [0052] The data storing layer DS may include a blocking insulating layer adjacent to the gate electrodes GP, a tunnel insulating layer adjacent to the channel semiconductor layer CP) each extending in the first direction (Hwang, FIG. 18, vertical Z-direction) outside the first semiconductor film (Hwang, FIG. 18, vertical structures VS) through the first stacked body (Hwang, FIG. 18, stacked body including GP and 120),
the second chip (Hwang, FIG. 18, C2; the chip bonded above the first chip including GP / 120 / VS / 10S; [0031], second semiconductor chip C2; [0044] gate electrodes GP, insulating layers 120; [0050] vertical structures VS; [0062] second body conductive layer 10S) includes a second stacked body (Hwang, FIG 18, stacked body including GP and 120; [0044] electrode structures ST including gate electrodes GP and insulating layers 120) in which a plurality of second conductive layers (Hwang, FIG. 18, gate electrodes GP; [0044] gate electrodes GP) are stacked in the first direction (Hwang, FIG. 18, vertical Z-direction D3) through a second insulating layer (Hwang, FIG. 18, insulating layers 120; [0044] insulating layers 120), a plurality of second semiconductor films (Hwang, FIG. 18, vertical structures VS; [0050] vertical structures VS extending vertically) each extending in the first direction through the second stacked body (Hwang, FIG. 18, stacked body including GP and 120), and a plurality of second insulating films (Hwang, FIG. 3A, 3B, 139, blocking insulating layer, tunnel insulating layer; [0051] As shown in FIGS. 3A and 3B, each of the vertical structures VS may include a buried insulating layer 139; [0052] The data storing layer DS may include a blocking insulating layer adjacent to the gate electrodes GP, a tunnel insulating layer adjacent to the channel semiconductor layer CP) each extending in the first direction outside the second semiconductor film (Hwang, FIG. 18, vertical structures VS) through the second stacked body (Hwang, FIG. 18, stacked body including GP and 120),
each of the first conductive layers (Hwang, FIG. 18, gate electrodes GP) longitudinally extends in a second direction (Hwang, FIG. 18, horizontal X-direction D2; [0046] gate electrodes GP horizontally extending) perpendicular to the first direction (Hwang, FIG. 18, vertical Z-direction D3),
each of the second conductive layers (Hwang, FIG. 18, gate electrodes GP) longitudinally extends in the second direction (Hwang, FIG. 18, horizontal X-direction D2), and
the fourth chip (Hwang, FIG. 18, the top chip including 193 / ML / PL / BL; [0060] protection layer 193; [0059] upper interconnection lines ML; [0043] peripheral line PL; [0026] bit lines BL) includes a plurality of line patterns (Hwang, FIG. 18, upper interconnection lines ML; [0059] upper interconnection lines ML; [0043] peripheral lines PL) each extending in the second direction (Hwang, FIG. 18, horizontal X-direction D2) and aligned with each other in a third direction (Hwang, FIG. 18, horizontal Y-direction D1) perpendicular to the first direction (Hwang, FIG. 18, vertical Z-direction D3) and the second direction (Hwang, FIG. 18, horizontal X-direction D2), and a plurality of electrodes ( Hwang, FIG. 18, PL; [0043], Peripheral lines PL ) disposed on one end of the plurality of line patterns (Hwang, FIG. 18, upper interconnection lines ML; [0059] upper interconnection lines ML; [0043] peripheral lines PL) along the second direction (Hwang, FIG. 18, horizontal X-direction D2) when viewed from the top, wherein each of the plurality of electrodes ( Hwang, FIG. 18, PL; [0043], Peripheral lines PL ) is coupled to a corresponding one of a plurality of plugs ( Hwang, FIG. 18, 165; [0043], Peripheral contacts 165 ).
Hwang fails to disclose:
the plurality of line patterns are aligned with portions of sidewalls of the plurality of plugs along the third direction.
However, Kim teaches:
the plurality of line patterns ( Kim, FIG. 18, FIG. 19A, FIG. 19B, EP; [0097], electrode portions EP ) are aligned with portions of sidewalls of the plurality of plugs ( Kim, FIG. 17, DS; [0061], The dummy structures DS may physically support the stack structure ST on the connection region CTR; [0060], The dummy structures DS may be adjacent to the contact plugs CP but may be spaced apart from the contact plugs CP; FIG. 20A, CP1; [0106], First contact plugs CP1 ) along the third direction.
Hwang and Kim are both considered to be analogous to the claimed invention because they are forming semiconductor memory device. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Hwang ( FIG. 18, upper interconnection lines ML, peripheral lines PL, peripheral contacts 165 ), to incorporate the teachings of Kim ( FIG. 18, FIG. 19A, FIG. 19B, electrode portions EP; FIG. 17, dummy structures DS ), to implement the plurality of line patterns are aligned with portions of sidewalls of the plurality of plugs along the third direction. Doing so would provide specific layout for the line patterns and plugs, and therefore the physical support or strength of the stack structure in semiconductor memory device can be improved.
Regarding Claim 2 ( Original ), Hwang and Kim teach the semiconductor memory device as claimed in claim 1, on which this claim is dependent, Hwang further teaches: wherein
the third chip (Hwang, FIG. 18, C1; the chip bonded above the second chip on a side opposite to the first chip including GP / 120 / VS / 10F; [0031], first semiconductor chip C1; [0044] gate electrodes GP, insulating layers 120; [0050] vertical structures VS; [0062] first body conductive layer 10F) includes a plurality of bit lines (Hwang, FIG. 18, BL; [0058] bit lines BL) each extending in the second direction (Hwang, FIG 18, horizontal X-direction D2) and aligned with each other in the first direction (Hwang, FIG 18, vertical Z-direction D3), and
a width of each of the line patterns (Hwang, FIG 18, upper interconnection lines ML; [0059] upper interconnection lines ML; [0043] peripheral lines PL) is greater (Hwang, FIG. 18, “width of ML” greater than “width of BL”) than a width of each of the plurality of bit lines (Hwang, FIG. 18, BL; [0058] bit lines BL) (In semiconductor memory device design, upper interconnection lines ML typically have greater thickness / width to reduce resistance and enhance electrical properties, meaning film thickness / width greater than underlying bit lines BL).
Regarding Claim 3 ( Original ), Hwang and Kim teach the semiconductor memory device as claimed in claim 1, on which this claim is dependent, Hwang further teaches: wherein
the third chip (Hwang, FIG. 18, C1; the chip bonded above the second chip on a side opposite to the first chip including GP / 120 / VS / 10F; [0031], first semiconductor chip C1; [0044] gate electrodes GP, insulating layers 120; [0050] vertical structures VS; [0062] first body conductive layer 10F) includes a plurality of bit lines (Hwang, FIG. 18, BL; [0058] bit lines BL) each extending in the second direction (Hwang, FIG. 18, horizontal X-direction D2) and aligned with each other in the first direction (Hwang, FIG. 18, vertical Z-direction D3), and
a film thickness of each of the line patterns is greater (Hwang, FIG. 18, “film thickness of ML” greater than “film thickness of BL”) than a film thickness of each of the plurality of bit lines (Hwang, FIG. 18, BL; [0058] bit lines BL).
Regarding Claim 4 ( Original ), Hwang and Kim teach the semiconductor memory device as claimed in claim 1, on which this claim is dependent, Hwang further teaches: wherein
the plurality of line patterns (Hwang, FIG 18, upper interconnection lines ML; [0059] upper interconnection lines ML; [0043] peripheral lines PL) are disposed at a position corresponding to at least one of the first stacked body (Hwang, FIG 18, in C1, stacked body including GP and 120; [0044] electrode structures ST including gate electrodes GP and insulating layers 120) or the second stacked body (Hwang, FIG 18, in C2, stacked body including GP and 120; [0044] electrode structures ST including gate electrodes GP and insulating layers 120).
Regarding Claim 5 ( Currently Amended ), Hwang and Kim teach the semiconductor memory device as claimed in claim 1, on which this claim is dependent, Hwang further teaches: wherein
each of the plurality of electrodes ( Hwang, FIG. 18, PL; [0043], Peripheral lines PL ) has a top surface exposed at an opening
Regarding Claim 6 ( Currently Amended ), Hwang and Kim teach the semiconductor memory device as claimed in claim 5, on which this claim is dependent, Hwang further teaches: wherein
the fourth chip (Hwang, FIG. 18, the top chip including 193 / ML / PL / BL; [0060] protection layer 193; [0059] upper interconnection lines ML; [0043] peripheral line PL; [0026] bit lines BL) further includes a conductive film ( Hwang, FIG. 18, ML on the top left ) disposed above the plurality of line patterns( Hwang, FIG. 18, BL on the top left ), the conductive film and the electrode ( Hwang, FIG. 18, ML on the top right ) being disposed at a same depth within the fourth chip.
Regarding Claim 7 ( Original ), Hwang and Kim teach the semiconductor memory device as claimed in claim 1, on which this claim is dependent, Hwang further teaches: wherein
the fourth chip (Hwang, FIG. 18, the top chip including 193 / ML / PL / BL; [0060] protection layer 193; [0059] upper interconnection lines ML; [0043] peripheral line PL; [0026] bit lines BL) further includes an insulating film (Hwang, FIG. 18, IL2, 193; [0043] Interlayered insulating layers IL1 and IL2, … interlayered insulating layers IL1 and IL2 may be formed of or include at least one of a silicon oxide layer and/or a silicon oxynitride layer; [0060], protection layer 193, … protection layer 193 may be formed of or include silicon nitride or silicon oxynitride) disposed around the plurality of line patterns (Hwang, FIG. 18, upper interconnection lines ML; [0059] upper interconnection lines ML; [0043] peripheral lines PL), and
the plurality of line patterns (Hwang, FIG. 18, upper interconnection lines ML; [0059] upper interconnection lines ML … upper interconnection lines ML and the upper contacts 191 may be formed of or include at least one of metals or conductive metal nitrides; [0043] peripheral lines PL … peripheral line PL may be formed of or include at least one of conductive materials (e.g., doped silicon, metals, and conductive metal nitrides)) have compositions different from a composition of the insulating film (Hwang, FIG. 18, IL2, 193; [0043] Interlayered insulating layers IL1 and IL2, … interlayered insulating layers IL1 and IL2 may be formed of or include at least one of a silicon oxide layer and/or a silicon oxynitride layer; [0060], protection layer 193, … protection layer 193 may be formed of or include silicon nitride or silicon oxynitride).
Regarding Claim 8 ( Original ), Hwang and Kim teach the semiconductor memory device as claimed in claim 1, on which this claim is dependent, Hwang further teaches: wherein
the fourth chip (Hwang, FIG. 18, the top chip including 193 / ML / PL / BL; [0060] protection layer 193; [0059] upper interconnection lines ML; [0043] peripheral line PL; [0026] bit lines BL) further includes an insulating film (Hwang, FIG. 18, IL2, 193; [0043] Interlayered insulating layers IL1 and IL2, … interlayered insulating layers IL1 and IL2 may be formed of or include at least one of a silicon oxide layer and/or a silicon oxynitride layer; [0060], protection layer 193, … protection layer 193 may be formed of or include silicon nitride or silicon oxynitride) disposed around the plurality of line patterns, and
the plurality of line patterns (Hwang, FIG. 18, upper interconnection lines ML; [0059] upper interconnection lines ML … upper interconnection lines ML and the upper contacts 191 may be formed of or include at least one of metals or conductive metal nitrides; [0043] peripheral lines PL … peripheral line PL may be formed of or include at least one of conductive materials (e.g., doped silicon, metals, and conductive metal nitrides)) have film densities different from a film density of the insulating film (Hwang, FIG. 18, IL2, 193; [0043] Interlayered insulating layers IL1 and IL2, … interlayered insulating layers IL1 and IL2 may be formed of or include at least one of a silicon oxide layer and/or a silicon oxynitride layer; [0060], protection layer 193, … protection layer 193 may be formed of or include silicon nitride or silicon oxynitride) ( Metal nitrides, for example, while titanium nitride (TiN) is significantly denser at 5.21 g/cm³. Molybdenum nitride (Mo2N) has a density of 9.06 g/cm³. Silicon nitride (Si3N4) has a density of 3.17 g/cm³. The density of silicon dioxide (SiO2) varies depending on its crystalline structure. Crystalline forms like quartz have a density of around 2.65 g/cm³, while amorphous forms, like fused silica, have a density of about 2.2 g/cm³ ).
Regarding Claim 9 ( Original ), Hwang and Kim teach the semiconductor memory device as claimed in claim 1, on which this claim is dependent, Hwang further teaches: wherein
the first conductive layer (Hwang, FIG. 18, gate electrodes GP; [0044] gate electrodes GP) further extends in the third direction (Hwang, FIG. 18, horizontal Y-direction D1; [0046] Each of the gate electrodes GP in the electrode structures ST may extend in a first direction D1).
Regarding Claim 10 ( Original ), Hwang and Kim teach the semiconductor memory device as claimed in claim 1, on which this claim is dependent, Hwang further teaches: wherein
the second conductive layer (Hwang, FIG. 18, gate electrodes GP; [0044] gate electrodes GP) further extends in the third direction (Hwang, FIG. 18, horizontal Y-direction D1; [0046] Each of the gate electrodes GP in the electrode structures ST may extend in a first direction D1).
Regarding Claim 11 ( Original ), Hwang and Kim teach the semiconductor memory device as claimed in claim 1, on which this claim is dependent, Hwang further teaches: wherein
the first stacked body (Hwang, FIG. 18, in C1, stacked body including GP and 120; [0044] electrode structures ST including gate electrodes GP and insulating layers 120) has a first isosceles trapezoidal shape with a first side extending longer in the second direction (Hwang, FIG. 18, horizontal X-direction D2) than a second side, wherein the second stacked body (Hwang, FIG 18, in C2, stacked body including GP and 120; [0044] electrode structures ST including gate electrodes GP and insulating layers 120) has a second isosceles trapezoidal shape with a third side extending longer in the second direction (Hwang, FIG. 18, horizontal X-direction D2) than a fourth side ( Hwang, [0063], The first and second semiconductor chips C1 and C2 are illustrated to have mirror symmetry with the interface interposed therebetween, but the inventive concepts is not limited thereto. For example, positions of the cell array region and peripheral circuit region CR and PR and shapes and positions of the gate electrodes GP, in each of the first and second semiconductor chips C1 and C2, may be variously changed ).
Regarding Claim 12 ( Original ), Hwang and Kim teach the semiconductor memory device as claimed in claim 11, on which this claim is dependent, Hwang further teaches: wherein
the second side (Hwang, FIG. 18, in C1, stacked body including GP and 120, the bottom side) faces the third side (Hwang, FIG 18, in C2, stacked body including GP and 120, the top side).
Regarding Claim 13 ( Original ), Hwang and Kim teach the semiconductor memory device as claimed in claim 11, on which this claim is dependent, Hwang further teaches: wherein
the first side (Hwang, FIG. 18, in C1, stacked body including GP and 120, the top side) faces the third side (Hwang, FIG 18, in C2, stacked body including GP and 120, the top side).
Regarding Independent Claim 14 ( Currently Amended ), Hwang teaches a semiconductor memory device, comprising:
a first chip (Hwang, FIG. 18, the bottom chip including 193 / ML / PL / BL; [0060] protection layer 193; [0059] upper interconnection lines ML; [0043] peripheral line PL; [0026] bit lines BL);
a second chip (Hwang, FIG. 18, C2; the chip bonded above the first chip including GP / 120 / VS / 10S; [0031], second semiconductor chip C2; [0044] gate electrodes GP, insulating layers 120; [0050] vertical structures VS; [0062] second body conductive layer 10S) bonded to the first chip;
a third chip (Hwang, FIG. 18, C1; the chip bonded above the second chip on a side opposite to the first chip including GP / 120 / VS / 10F; [0031], first semiconductor chip C1; [0044] gate electrodes GP, insulating layers 120; [0050] vertical structures VS; [0062] first body conductive layer 10F) bonded to the second chip on a side opposite to the first chip; and
a fourth chip bonded to the third chip on a side opposite to the second chip, wherein
(Hwang, FIG. 18, the top chip including 193 / ML / PL / BL; [0060] protection layer 193; [0059] upper interconnection lines ML; [0043] peripheral line PL; [0026] bit lines BL)
the third chip (Hwang, FIG. 18, C1; the chip bonded above the second chip on a side opposite to the first chip including GP / 120 / VS / 10F; [0031], first semiconductor chip C1; [0044] gate electrodes GP, insulating layers 120; [0050] vertical structures VS; [0062] first body conductive layer 10F) includes a first stacked body (Hwang, FIG. 18, stacked body including GP and 120; [0044] electrode structures ST including gate electrodes GP and insulating layers 120), the first stacked body including a plurality of first conductive layers (Hwang, FIG. 18, gate electrodes GP; [0044] gate electrodes GP) stacked in a first direction (Hwang, FIG. 18, vertical Z-direction D3),
the second chip (Hwang, FIG. 18, C2; the chip bonded above the first chip including GP / 120 / VS / 10S; [0031], second semiconductor chip C2; [0044] gate electrodes GP, insulating layers 120; [0050] vertical structures VS; [0062] second body conductive layer 10S) includes a second stacked body (Hwang, FIG 18, stacked body including GP and 120; [0044] electrode structures ST including gate electrodes GP and insulating layers 120), the second stacked body including a plurality of second conductive layers (Hwang, FIG. 18, gate electrodes GP; [0044] gate electrodes GP) stacked in the first direction (Hwang, FIG. 18, vertical Z-direction D3),
the first conductive layer (Hwang, FIG. 18, gate electrodes GP) longitudinally extends in a second direction (Hwang, FIG. 18, horizontal X-direction D2) perpendicular to the first direction (Hwang, FIG. 18, vertical Z-direction D3),
the second conductive layer (Hwang, FIG. 18, gate electrodes GP) longitudinally extends in the second direction (Hwang, FIG. 18, horizontal X-direction D2), and
the fourth chip (Hwang, FIG. 18, the top chip including 193 / ML / PL / BL; [0060] protection layer 193; [0059] upper interconnection lines ML; [0043] peripheral line PL; [0026] bit lines BL) includes a plurality of line patterns (Hwang, FIG. 18, upper interconnection lines ML; [0059] upper interconnection lines ML; [0043] peripheral lines PL) each extending in the second direction (Hwang, FIG. 18, horizontal X-direction D2) and aligned with each other in a third direction (Hwang, FIG. 18, horizontal Y-direction D1) perpendicular to the first direction (Hwang, FIG. 18, vertical Z-direction D3) and the second direction (Hwang, FIG. 18, horizontal X-direction D2), and the fourth chip further includes a plurality of electrodes ( Hwang, FIG. 18, PL; [0043], Peripheral lines PL ) disposed on one end of the plurality of line patterns (Hwang, FIG. 18, upper interconnection lines ML; [0059] upper interconnection lines ML; [0043] peripheral lines PL) along the second direction (Hwang, FIG. 18, horizontal X-direction D2) when viewed from the top, wherein each of the plurality of electrodes ( Hwang, FIG. 18, PL; [0043], Peripheral lines PL ) is coupled to a corresponding one of a plurality of plugs ( Hwang, FIG. 18, 165; [0043], Peripheral contacts 165 ).
Hwang fails to disclose:
the plurality of line patterns are aligned with portions of sidewalls of the plurality of plugs along the third direction.
However, Kim teaches:
the plurality of line patterns ( Kim, FIG. 18, FIG. 19A, FIG. 19B, EP; [0097], electrode portions EP ) are aligned with portions of sidewalls of the plurality of plugs ( Kim, FIG. 17, DS; [0061], The dummy structures DS may physically support the stack structure ST on the connection region CTR; [0060], The dummy structures DS may be adjacent to the contact plugs CP but may be spaced apart from the contact plugs CP; FIG. 20A, CP1; [0106], First contact plugs CP1 ) along the third direction.
Hwang and Kim are both considered to be analogous to the claimed invention because they are forming semiconductor memory device. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Hwang ( FIG. 18, upper interconnection lines ML, peripheral lines PL, peripheral contacts 165 ), to incorporate the teachings of Kim ( FIG. 18, FIG. 19A, FIG. 19B, electrode portions EP; FIG. 17, dummy structures DS ), to implement the plurality of line patterns are aligned with portions of sidewalls of the plurality of plugs along the third direction. Doing so would provide specific layout for the line patterns and plugs, and therefore the physical support or strength of the stack structure in semiconductor memory device can be improved.
Regarding Claim 15 ( Original ), Hwang and Kim teach the semiconductor memory device as claimed in claim 14, on which this claim is dependent, Hwang further teaches: wherein:
the first stacked body (Hwang, FIG. 18, stacked body including GP and 120; [0044] electrode structures ST including gate electrodes GP and insulating layers 120) further includes:
a plurality of first semiconductor films (Hwang, FIG. 18, vertical structures VS; [0050] vertical structures VS extending vertically) each extending in the first direction (Hwang, FIG. 18, vertical Z-direction D3), and a plurality of first insulating films (Hwang, FIG. 3A, 3B, 139, blocking insulating layer, tunnel insulating layer; [0051] As shown in FIGS. 3A and 3B, each of the vertical structures VS may include a buried insulating layer 139; [0052] The data storing layer DS may include a blocking insulating layer adjacent to the gate electrodes GP, a tunnel insulating layer adjacent to the channel semiconductor layer CP) each extending in the first direction (Hwang, FIG. 18, vertical Z-direction D3) outside the first semiconductor film; and
the second stacked body (Hwang, FIG 18, stacked body including GP and 120; [0044] electrode structures ST including gate electrodes GP and insulating layers 120) further includes:
a plurality of second semiconductor films (Hwang, FIG. 18, vertical structures VS; [0050] vertical structures VS extending vertically) each extending in the first direction (Hwang, FIG. 18, vertical Z-direction D3), and a plurality of second insulating films (Hwang, FIG. 3A, 3B, 139, blocking insulating layer, tunnel insulating layer; [0051] As shown in FIGS. 3A and 3B, each of the vertical structures VS may include a buried insulating layer 139; [0052] The data storing layer DS may include a blocking insulating layer adjacent to the gate electrodes GP, a tunnel insulating layer adjacent to the channel semiconductor layer CP) each extending in the first direction (Hwang, FIG. 18, vertical Z-direction D3) outside the second semiconductor film.
Regarding Claim 16 ( Original ), Hwang and Kim teach the semiconductor memory device as claimed in claim 14, on which this claim is dependent, Hwang further teaches: wherein:
the third chip (Hwang, FIG. 18, C1; the chip bonded above the second chip on a side opposite to the first chip including GP / 120 / VS / 10F; [0031], first semiconductor chip C1; [0044] gate electrodes GP, insulating layers 120; [0050] vertical structures VS; [0062] first body conductive layer 10F) includes a plurality of bit lines (Hwang, FIG. 18, BL; [0058] bit lines BL) each extending in the second direction (Hwang, FIG. 18, horizontal X-direction D2) and aligned with each other in the first direction (Hwang, FIG. 18, vertical Z-direction D3), and
a width of each of the line patterns (Hwang, FIG 18, upper interconnection lines ML; [0059] upper interconnection lines ML; [0043] peripheral lines PL) is greater than a width of each of the plurality of bit lines (Hwang, FIG. 18, BL; [0058] bit lines BL) (In semiconductor memory device design, upper interconnection lines ML typically have greater thickness / width to reduce resistance and enhance electrical properties, meaning film thickness / width greater than underlying bit lines BL).
Regarding Claim 17 ( Original ), Hwang and Kim teach the semiconductor memory device as claimed in claim 14, on which this claim is dependent, Hwang further teaches: wherein:
the third chip (Hwang, FIG. 18, C1; the chip bonded above the second chip on a side opposite to the first chip including GP / 120 / VS / 10F; [0031], first semiconductor chip C1; [0044] gate electrodes GP, insulating layers 120; [0050] vertical structures VS; [0062] first body conductive layer 10F) includes a plurality of bit lines (Hwang, FIG. 18, BL; [0058] bit lines BL) each extending in the second direction (Hwang, FIG. 18, horizontal X-direction D2) and aligned with each other in the first direction (Hwang, FIG. 18, vertical Z-direction D3), and
a film thickness of each of the line patterns is greater (Hwang, FIG. 18, “film thickness of ML” greater than “film thickness of BL”) than a film thickness of each of the plurality of bit lines (Hwang, FIG. 18, BL; [0058] bit lines BL).
Response to Arguments
Applicant's remarks filed 11/13/2025 have been fully considered but they are not persuasive.
Applicant’s remarks regarding ( Currently Amended ) Claims 1: on page 8, line 7, cited “ As shown in FIG. 5, the elements SP-1 to SP-3 and portions of the sidewalls of the elements CCs are aligned with one another along the Y-direction. Even applying Hwang to the present application (as asserted by the Office), no teaching or suggestion of the combination of these features in Hwang is found. Applicant submits that claim 1, as amended, is patentable and allowable over the prior art. ”.
Examiner’s response: please refer to claims xx in Claim Rejections - 35 USC § 103 of this office action, for instance, claim 1, cited “ Hwang fails to disclose:
the plurality of line patterns are aligned with portions of sidewalls of the plurality of plugs along the third direction.
However, Kim teaches:
the plurality of line patterns ( Kim, FIG. 18, FIG. 19A, FIG. 19B, EP; [0097], electrode portions EP ) are aligned with portions of sidewalls of the plurality of plugs ( Kim, FIG. 17, DS; [0061], The dummy structures DS may physically support the stack structure ST on the connection region CTR; [0060], The dummy structures DS may be adjacent to the contact plugs CP but may be spaced apart from the contact plugs CP; FIG. 20A, CP1; [0106], First contact plugs CP1 ) along the third direction.
Hwang and Kim are both considered to be analogous to the claimed invention because they are forming semiconductor memory device. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Hwang ( FIG. 18, upper interconnection lines ML, peripheral lines PL, peripheral contacts 165 ), to incorporate the teachings of Kim ( FIG. 18, FIG. 19A, FIG. 19B, electrode portions EP; FIG. 17, dummy structures DS ), to implement the plurality of line patterns are aligned with portions of sidewalls of the plurality of plugs along the third direction. Doing so would provide specific layout for the line patterns and plugs, and therefore the physical support or strength of the stack structure in semiconductor memory device can be improved. ”. Therefore, “ the elements SP-1 to SP-3 and portions of the sidewalls of the elements CCs are aligned with one another along the Y-direction ” is disclosed over Hwang, in view of Kim.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Da-Wei Lee whose telephone number is 703-756-1792. The examiner can normally be reached Monday thru Friday E.T..
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached on 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DA-WEI LEE/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817