DETAILED ACTION
The RCE filed July 22, 2026 has been entered. Claims 1-20 are pending. Claims 1, 8 and 16 are independent.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4-12 and 15-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Li (US 2022/0414444).
Regarding independent claims 1, 8 and 16, Li discloses a memory array used for computing-in-memory (CIM) (e.g., see FIGS. 4 and 8), comprising:
a bit cell array (400 / 800) including a plurality of bit cells, wherein each of the plurality of bit cells includes a first transistor and a second transistor (see EXMINER’S MARKUP below), and has a storage bit and operates at an operating voltage, and the plurality of storage bits are associated with a weight bit of a convolutional neural network (CNN) (e.g., para. 0040: … Convolutional neural network … the input for each node …) wherein the first transistor has a first first terminal and a first second terminal, and the second transistor has a second first terminal and a second second terminal (see EXMINER’S MARKUP below);
at least one word line (427, WL, and see para. 0064) electrically connected to the first first terminal of the first transistor of the bit cell array (see EXMINER’S MARKUP below), wherein the at least one of word line is associated with an input bit of the CNN, wherein the first transistor and the second transistor are serially electrically connected (see EXMINER’S MARKUP below);
at least one bit line (418, BL, and see para. 0064) electrically connected the first second terminal of the first transistor of to the bit cell array, wherein the plurality of bit cells are arranged along at least one of a bit line direction and a word line direction, each the at least one bit line has an electrical parameter (FIG. 8: 806 and 808, and see para. 0105), a first plurality of bit cells of the bit cell array are arranged along the bit line direction according to a first arrangement quantity, the memory array expands the input bit of the CNN (see e.g., para. 0124) to a plurality of input bits based on at least one of the first arrangement quantity and the operating voltage, and at least one of the first arrangement quantity and the operating voltage is a first weight associated with the first plurality of input bits; and
a reading circuit (410, ADC, and see para. 0093: a readout from the ADC) electrically connected to and sensing the electrical parameter of each the at least one bit line to obtain a multiplication and addition result of the plurality of input bits of the CNN and the corresponding weight bits thereof (see FIG. 4 and FIG. 8, and accompanying disclosure).
Further, regarding method claim 8, where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. Examiner has an authority to shift the burden to applicant and require applicant to either: (1) show the prior art memory device and the claimed memory device are not substantially identical; or (2) prove, by evidence, that the prior art memory device is not capable of performing the functions claimed. see MPEP 2112.01(I).
PNG
media_image1.png
504
970
media_image1.png
Greyscale
Regarding claims 4 and 15, which depends from claims 1 and 8, respectively, Li discloses the first arrangement quantity is positively correlated with the first weight of the plurality of input bits (see e.g., para. 0049: … an error would be … decrease if a weight were adjusted …).
Regarding claim 5, which depends from claim 1, Li discloses the reading circuit includes at least one capacitor corresponding to the at least one bit line to obtain the multiplication and addition result (see e.g., FIGS. 4-5, and accompanying disclosure).
Regarding claim 6, which depends from claim 1, Li discloses the memory array further includes an analog-to-digital conversion circuit serving as the reading circuit for converting the multiplication and addition result into a digital data (FIGS. 4 and 8, and accompanying disclosure, e.g., para. 0067: … accumulated charges …).
Regarding claim 7, which depends from claim 1, Li discloses the plurality of bit cells are arranged along the word line direction according to a second arrangement quantity; and the memory array expands the weight bit of the CNN into a plurality of weight bits based on the second arrangement quantity and the operation voltage, and the second arrangement quantity and the operation voltage is associated with a second weight of the plurality of weight bits (FIGS. 4 and 8, and accompanying disclosure).
Regarding claim 9, which depends from claim 8, Li discloses the plurality of bit cells are arranged along the word line direction according to a second arrangement quantity; and the method further includes steps of: expanding (e.g., para. 0124: … expand input features …) the weight bit of the CNN into a plurality of weight bits based on the second arrangement quantity and the operating voltage; and correlating (e.g., para. 0049: … a weight were adjusted …) the second arrangement quantity and the operating voltage with a second weight of the plurality of weight bits.
Regarding claim 10, which depends from claim 8, Li discloses the weight bit is associated with a single weight element of the CNN (e.g., para. 0057: … single point …; para. 0110: … a one-bit weight …).
Regarding claim 11, which depends from claim 8, Li discloses the input bit is associated with a single input element of the CNN (e.g., para. 0057: … single point …; para. 0110: … using a single column …).
Regarding claim 12, which depends from claim 8, Li discloses the memory array further includes a reading circuit electrically connected to the at least one bit line, and sensing an electrical parameter of the at least one bit line to obtain a multiplication and addition result of the plurality of input bits of the CNN and the corresponding weight bits thereof (FIGS. 4 and 8, and accompanying disclosure, e.g., para. 0067: … accumulated charges …).
Regarding claim 17, which depends from claim 16, Li discloses the direction is purely along a bit line direction, purely along a word line direction, or along both the word line direction and the bit line direction (FIGS. 4 and 7-8).
Regarding claim 18, which depends from claim 16, Li discloses the first parameter is associated with an input bit of a convolutional neural network (CNN); each of the bit cells has a storage bit associated with the second parameter, and the second parameter is associated with a weight bit of the CNN; the weight bit is associated with a single weight element of the CNN; and the input bit is associated with a single input element of the CNN (e.g., para. 0057: … single point …; para. 0110: … using a single column … a one-bit weight …).
Regarding claim 19, which depends from claim 16, Li discloses the first parameter is associated with an input bit of a convolutional neural network (CNN); the first quantity of the plurality of bit cells extends along a bit line direction; and the memory array expands (e.g., para. 0124: … expand input features …) the input bit of the CNN to a plurality of input bits according to at least one of the first quantity and the operating voltage, and at least one of the first quantity and the operating voltage is related to a first weight magnitude of the plurality of input bits (see FIGS. 4 and 8, and accompanying disclosure).
Regarding claim 19, which depends from claim 16, Li discloses the second parameter is associated with a weight bit of a convolutional neural network (CNN); the bit cell array further includes a second quantity of bit cells extending along a word line direction; and the memory array expands the weight bit of the CNN to a plurality of weight bits according to at least one of the second quantity and the operating voltage, and at least one of the second quantity and the operating voltage is related to a second weight magnitude of the plurality of weight bits (see FIGS. 4 and 8, and accompanying disclosure).
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 13 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Li (US 2022/0414444).
Regarding claims 2 and 13, Li teaches the limitations of claim 1 and 8, respectively.
Li further teaches the first first terminal and the second first terminal are gate electrodes (see FIG. 4: 413 and 411 and EXMINER’S MARKUP above); the first second terminal and the second second terminal are drain electrodes (see FIG. 4 and EXMINER’S MARKUP above); and the electrical parameter includes at least one of a current, a charge, and a voltage (e.g., para. 0067: … any charges on capacitors (which is based on corresponding bitcell (weight) …values) … the voltage values …; i.e., it implies the weight in weigh parameters includes charges on capacitors).
Li is silent with respect to the first and the second transistors are NMOS transistors.
However, a memory bit cell composed of serially connected NMOS transistors, used in computing-in-memory, is a well-known technology for a type of memory for its purpose.
For support, of the above asserted facts, see for example, Wang et al. (US 2021/0133549), e.g., FIGS. 6A-6E, e.g., 620 NMOS transistor (which is a claimed first transistor coupled to bit line and controlled by word line) and serially connected NMOS transistor 632 (or 630 or 624); Wang et al. (US 2021/0124793), e.g., FIG. 5; Li et al. (US 2024/0005977), e.g., FIG. 4 and accompanying disclosure.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a memory bit cell composed of serially connected MOS transistors because these conventional technology are well established in the art of the memory devices.
Claims 3 and 14 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Li (US 2022/0414444) in view of e.g., Pasotti et al. (US 12,211,582).
Regarding claims 3 and 14, Li further teaches the memory array further includes at least one voltage regulation circuit to provide the operating voltage; and the operating voltage has a magnitude which is positively correlated with the first weight of the plurality of input bits (see e.g., para. 0049: … an error would be … decrease if a weight were adjusted …).
Li does not explicitly disclose voltage regulation circuit in memory.
However, voltage regulator circuit in memory device is a well-known technology for a type of memory circuit for its purpose.
For support, of the above asserted facts, see for example, Pasotti et al., e.g., FIG. 2B, and accompanying disclosure, e.g., col. 7, lines 2-7: … Transistor 40 functions as a voltage regulator to bias the bit line BL …
Li and Pasotti are analogous art because they both are directed to CIM device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Li with the specified features of Pasotti because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Pasotti et al. to the teaching of Li such that a memory, as taught by Li, utilizes a voltage regulator circuit, as taught by Pasotti et al., for the purpose of generating stable reference voltage, and further these conventional technology are well established in the art of the memory devices.
Response to Arguments
Applicant’s RCE filed 07/22/2026, with respect to the rejection(s) of claims 1-20 under 35 USC 102 and 103, have been fully considered but are not persuasive. See the art rejections above for more details. Therefore, it is respectfully submitted that the examiner maintains the rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUNG IL CHO whose telephone number is (571)270-0137. The examiner can normally be reached M-Th, 7:30AM-5PM; Every other F, 7:30AM-4PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander G Sofocleous can be reached at 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SUNG IL CHO/Primary Examiner, Art Unit 2825
Prosecution Insights