Prosecution Insights
Last updated: July 17, 2026
Application No. 18/175,985

DIE BENDING STIFFNESS MODIFICATION THROUGH GROOVING

Non-Final OA §102§103
Filed
Feb 28, 2023
Examiner
PHAM, LONG
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
International Business Machines Corporation
OA Round
2 (Non-Final)
92%
Grant Probability
Favorable
2-3
OA Rounds
0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 92% — above average
92%
Career Allowance Rate
1515 granted / 1655 resolved
+23.5% vs TC avg
Moderate +6% lift
Without
With
+5.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
38 currently pending
Career history
1688
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
56.5%
+16.5% vs TC avg
§102
24.1%
-15.9% vs TC avg
§112
9.4%
-30.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1655 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 2, 3, 4, 5, 6, and 8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Seng (US pub 20050093174). With respect to claim 1, Seng teaches a semiconductor structure, comprising (see figs. 1-14, particularly figs. 3, 5, 9 and 10, 11-14): a packaging substrate 150; a lid 182; and a first semiconductor die 110,500 between the packaging substrate and the lid, comprising: a frontside (bottom) packaged toward the packaging substrate, comprising semiconductor devices 520; and a backside (top), opposite the frontside, comprising grooves 522, 524,530 over the semiconductor devices that are less than a thickness of the first semiconductor die. With respect to claim 2, Seng teaches the grooves comprise first parallel grooves 522 along a first direction (lateral, x). See fig. 10 and associated text. With respect to claim 3, Seng teaches the grooves comprise second parallel grooves 524 along a second direction (vertical, y). See fig. 10 and associated text. With respect to claim 4, Seng teaches the first direction is perpendicular to the second direction. See fig. 10 and associated text. With respect to claim 5, Seng teaches the backside comprises a clean region 520 without the grooves. See fig. 10 and associated text. With respect to claim 6, Seng teaches the grooves comprise a depth h that is greater than half of the thickness T of the semiconductor die. See fig. 5 and associated text. With respect to claim 8, Seng teaches wherein the thickness of the semiconductor die varies across the semiconductor die (areas without grooves having greater thickness and areas with groove having less thickness). See fig. 10 and associated text. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Seng (US pub 20050093174). With respect to claim 10, Seng teaches a single die but fail to teach the die comprises stacked dies. However, the use of stacked dies to increase device density is well-known in semiconductor art. Claim(s) 16, 17, and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Seng (US pub 20050093174). With respect to claim 16, Seng teaches a semiconductor structure, comprising (see figs. 1-14, particularly figs. 3, 5, 9 and 10, 11-14): a semiconductor die 110,500, comprising: a first section comprising first grooves 522, 530 cut into a backside (bottom) of the semiconductor die over a semiconductor device 520; a second section comprising second grooves 524, 530 cut into the backside of the semiconductor die; and a clean region 520 comprising no grooves. With respect to claim 17, Seng teaches a difference between the first grooves and the second grooves, wherein the difference is selected from the group consisting of: depth of the grooves, pitch of the grooves, angle of the grooves (522 vertical whereas 524 is lateral), length of the grooves, width of the grooves, and curve of the grooves. See figs. 3, 5, 9 and 10 and associated text. With respect to claim 20, Seng teaches the first grooves comprise a depth h that is greater than half of a thickness T of the semiconductor die. See figs. 3, 5, 9 and 10 and associated text. Allowable Subject Matter Claims 7, 9, and 18-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Response to Arguments Applicant's arguments filed 3/16/26 have been fully considered but they are not persuasive. See the above rejections. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to LONG PHAM whose telephone number is (571)272-1714. The examiner can normally be reached Mon-Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. LONG . PHAM Examiner Art Unit 2823 /LONG PHAM/Primary Examiner, Art Unit 2897
Read full office action

Prosecution Timeline

Feb 28, 2023
Application Filed
Dec 17, 2025
Non-Final Rejection mailed — §102, §103
Mar 03, 2026
Interview Requested
Mar 10, 2026
Applicant Interview (Telephonic)
Mar 10, 2026
Examiner Interview Summary
Mar 16, 2026
Response Filed
May 28, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12685219
PACKAGE COMPRISING A CHIPLET LOCATED BETWEEN AN INTEGRATED DEVICE AND A METALLIZATION PORTION
3y 10m to grant Granted Jul 14, 2026
Patent 12685214
SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES
3y 7m to grant Granted Jul 14, 2026
Patent 12685213
SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR PACKAGE
3y 2m to grant Granted Jul 14, 2026
Patent 12685233
THREE-DIMENSIONAL STACKING SEMICONDUCTOR ASSEMBLIES WITH NEAR ZERO BOND LINE THICKNESS
2y 0m to grant Granted Jul 14, 2026
Patent 12677686
Electronic Package with Components Mounted at Two Sides of a Layer Stack
3y 9m to grant Granted Jul 07, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

2-3
Expected OA Rounds
92%
Grant Probability
97%
With Interview (+5.5%)
2y 3m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 1655 resolved cases by this examiner. Grant probability derived from career allowance rate.

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