DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant election of group I, species I, claims 1-13 and 31-33, without traverse is acknowledged. Claims 14-30 are withdrawn from consideration.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-13 and 31-33 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The terms “first, second and third” in Claim 1 are relative terms which render the claim indefinite. The terms “first, second and third” are not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. In the instant case and applicant disclose a multilayered source/drain layers that are stacked vertically, however, the terms first, second and third do not identify the counting sequence by which the layers are stacked, top to bottom or bottom to top. Examiner will consider that count numbers first – third or any other sequence for that matter. While the claim are interpreted in light of the disclosure, importing limitation from the disclosure is impermissible and claims must stand on their own. Applicant clarification is required.
Claim 3 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In the instant case, Claim 3 discloses “wherein the first source/drain layer in each memory cell layer and the third source/drain layer in the memory cell layer below the each memory cell layer are the same layer;
and/or wherein the third source/drain layer in each memory cell layer and the first source/drain layer in the memory cell layer above the each memory cell layer are the same layer.” It is not clear what is meant by first and third source/drain layers are the same; is meant for same material? Or same functionality? Particularly they are not supposedly made the same physical disposition by the fact they’re stacked layers. Examiner will consider the if the stacked source/drain layers are made of the same material, the claim limitations will be met. Applicant clarification is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipate by Or-Bach et al. (US 2020/0194416), (hereinafter, Or-Bach).
RE Claim 1, Or-Bach discloses in FIGS. 4-5 a three-dimensional NOR-type memory array including vertical word lines and discrete memory elements and methods of manufacture. Or-Bach discloses a 3D NOR-type memory device, comprising:
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at least one memory cell layer disposed on a substrate [abstract], wherein the at least one memory cell layer comprises a first source/drain layer 420, a first channel layer 421, a second source/drain layer 420, a second channel layer 421, and a third source/drain layer 420 that are stacked;
at least one gate stack 404 that extends vertically with respect to the substrate to pass through the at least one memory cell layer, referring to FIG. 4A, wherein the at least one gate stack 404/402 comprises a gate conductor layer 404 and a memory functional layer 402 “charge storage stack/ONO” [0110] disposed between the gate conductor layer 404 and the at least one memory cell layer, and a memory cell is defined at an intersection of the at least one gate stack 404/402 and the at least one memory cell layer, referring to FIG. 4A and 5E. It is noted that the source/drain 420/channel 421/gate 404 and ONO layer 402 represent a “junction-less transistor JLT” and is a memory cell 0067];
at least one bit line BL1 electrically connected to the second source/drain layer in the at least one memory cell layer, by virtue of connecting to a source layer 420, referring to FIG. 5E; and
at least one source line SL1, SL2 or SL3 electrically connected to the first source/drain layer 420 and the third source/drain layer 420 in the at least one memory cell layer, since one source lines SLI or SL2 or SL3 is connected to at least 3 layers of source/drain layer 420 simultaneously, referring to FIG. 5E [0123, 0124 and 0129], hence meeting the claimed limitation.
RE Claim 2, Or-Bach discloses in FIGS. 4-5 a three-dimensional NOR-type memory array including vertical word lines and discrete memory elements and methods of manufacture. It is noted that the source/drain 420/channel 421/gate 404 and ONO layer 402 represent a junction-less transistor and is a memory cell 0067]. Or-Bach discloses a 3D NOR-type memory device [abstract and 0066], comprising:
at least one memory cell layer “NOR memory” disposed on a substrate [abstract], wherein the at least one memory cell layer comprises a first source/drain layer 420, a first channel layer 421, a second source/drain layer 420, a second channel layer 421, and a third source/drain layer 420 that are stacked, based on the alternately stacked 420/421in FIG. 4B; at least one gate stack 404/402 that extends vertically with respect to the substrate to pass through the at least one memory cell layer, referring to FIGS. 4A-4B and 5E,
wherein the at least one gate stack 404/402 comprises a gate conductor layer 404 and a memory functional layer 402 “charge storage stack/ONO” [0110] disposed between the gate conductor layer and the at least one memory cell layer, referring to FIGS. 4A and 5E, and
a memory cell is defined at an intersection of the at least one gate stack 404/402 and the at least one memory cell layer referring to FIGS. 4A and 5E;
at least two bit lines RBL3,RBL2/LBL3,LBL2 respectively electrically connected to the first source/drain layer and the third source/drain layer in the at least one memory cell layer, since each bit line is simultaneously connected to the stair-shaped source/drain regions 420, referring to FIG. 5E [0123, 0124 and 0129]; and
at least one source line SL1 electrically connected to the second source/drain layer in the at least one memory cell layer, referring to FIGS. 4C and 5E.
RE Claim 3, Or-Bach discloses NOR-type memory device, wherein the at least one memory cell layer comprises a plurality of memory cell layers, 421/420 “source/drain-channel” stacked layered structure, and
wherein the first source/drain layer 420 in each memory cell layer and the third source/drain layer 420 in the memory cell layer below the each memory cell layer are the same layer, since the source/drain stacked layers are all formed on doped silicon [0111], the claimed limitation is met;
and/or wherein the third source/drain layer in each memory cell layer and the first source/drain layer in the memory cell layer above the each memory cell layer are the same layer. Since the stacked source/drain layers 420 are made from the same silicon material, the claimed limitations are met.
RE Claim 4, Or-Bach discloses NOR-type memory device, wherein the first source/drain layer 420, the first channel layer 421, the second source/drain layer 420, the second channel layer 421, and the third source/drain layer 420 in the at least one memory cell layer “junction-less transistor JLT” are in direct contact with each other, referring to FIG. 4A and 5E, and
adjacent memory cell layers are in direct contact with each other, referring to FIG. 4A and 5E.
RE Claim 5, Or-Bach discloses NOR-type memory device, wherein a first cell composition device “junction-less transistor JLT” is defined at an intersection of the at least one gate stack 404/402 with respect to the first source/drain layer 420, the first channel layer 421, and the second source/drain layer 420 in the at least one memory cell layer “junction-less transistor JLT”, referring to FIGS. 33D and 37D [0067, 0069].
a second cell composition device is defined at an intersection of the at least one gate stack 404/402 with respect to the second source/drain layer 420, the second channel layer 421, and the third source/drain layer 420 in the at least one memory cell layer “junction-less transistor JLT”, and the first cell composition device “junction-less transistor JLT” and the second cell composition device “junction-less transistor JLT” are connected in parallel to each other to define a corresponding memory cell [0216]. Since the memory block 1602 are accessed in parallel, the first and second cell composition devices are connected in parallel, hence the claimed limitation is met.
RE Claim 6, Or-Bach discloses NOR-type memory device, further comprising:
at least one word line WL; and
at least one select transistor 3366 “vertical NPN transistor” which is disposed on the at least one gate stack respectively and is electrically connected between the at least one word line WL and the at least one gate stack 404/402, referring to FIGS. 33A-D and [0166, 0285, 0346].
RE Claim 7, Or-Bach discloses NOR-type memory device, wherein the at least one select transistor 3366 comprises an active layer “p-layer” self-aligned with an above portion of the at least one gate stack 404/402 and a select gate stack 3366 surrounding a periphery of the active layer “p-layer”, referring to FIG. 33D.
RE Claim 8, Or-Bach discloses NOR-type memory device, wherein the active layer “p-layer” of the at least one select transistor 3366 comprises a bottom portion extending at a top portion “vertical NPN” 3306 of the at least one gate stack and a side portion extending from the bottom portion, and
an outer wall of the side portion of the active layer is substantially coplanar to an outer wall of the at least one gate stack 404/402, referring to FIG. 33D.
RE Claim 9, Or-Bach discloses NOR-type memory device, wherein the at least one select transistor 3366 comprises a plurality of select transistors, referring to FIG. 33D, the plurality of select transistors 3366 are arranged in a plurality of rows in a first direction x-direction, referring to FIG. 33D, select gate stacks of select transistors 3366 in the same row extend continuously with each other in the first direction x-direction, referring to FIG. 33D, and
the at least one bit line BL and the at least one word line WL extend in a second direction y-direction intersecting the first direction x-direction, referring to FIG. 8B.
RE Claim 10, Or-Bach discloses NOR-type memory device, wherein at least one of the first source/drain layer 420, the first channel layer 421, the second source/drain layer 420, the second channel layer 421, and the third source/drain layer 420 comprises a single crystal semiconductor material “silicon” [0071,0073, 0087, 0089, 0092, 0098], since the layers are epitaxially grown, the claimed limitation is met.
RE Claim 11, Or-Bach discloses NOR-type memory device, wherein the first channel layer 421 and the second channel layer 421 comprise the single crystal semiconductor material [0071, 0073, 0087, 0089, 0092, 0098].
RE Claim 12, Or-Bach discloses NOR-type memory device, wherein the memory functional layer 402 comprises at least one of a charge trapping material “ONO” [0110, 0131] or a ferroelectric material.
RE Claim 13, Or-Bach discloses NOR-type memory device, wherein at least one of the first source/drain layer 420, the first channel layer 421, the second source/drain layer 420, the second channel layer 421, and the third source/drain layer 420 surrounds one or more of the at least one gate stack 404/402 in a transverse direction, referring to FIG. 4A.
RE Claim 31, Or-Bach discloses an electronic apparatus “3D-logic device”, low power system on a chip “SoC” [0136], wireless communication devices [0294] comprising the NOR-type memory device according to Claim 1 [0001].
RE Claim 32, Or-Bach discloses an electronic apparatus according, wherein the electronic apparatus comprises a smart phone, a personal computer, a tablet, an artificial intelligence device, a wearable device, a mobile power supply, an automotive electronic device, a communication device “wireless communication devices” [0294], an Internet of Things device, or a headphone.
RE Claim 33, Or-Bach discloses a method of operating the NOR-type memory device according to claim 1, comprising:
in one or more access operations of the NOR-type memory device, electrically connecting the at least one bit line as a bit line, and electrically connecting the at least one source line as a source line, referring to FIG. 5E [0123 and 1029]; and
in further one or more access operations of the NOR-type memory device, electrically connecting the at least one bit line as a source line, and electrically connecting the at least one source line as a bit line, referring to FIG. 11C [0185], since S/D line 1104 is used as a common source line, wherein traditional dual-bit-line pairs to run along the rows and serve as a shared source line, hence meet the claimed limitation.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. In the instant case, Cernea et al. (US 2020/0098779) disclose a staircase structures formed out of the active strips of a memory structure (e.g., a memory array having a three-dimensional arrangement of NOR memory strings) above a semiconductor substrate allows efficient electrical connections to semiconductor layers within the active strips.
RAJASHEKHAR et al. (US 2021/0242241) disclose a three-dimensional memory device includes an alternating stack of source layers and drain layers located over a substrate, a memory opening vertically extending through the alternating stack, a vertical word line located in the memory opening and vertically extending through each of the source layers and the drain layers of the alternating stack, discrete semiconductor channels contacting horizontal surfaces of a respective vertically neighboring pair of a source layer of the source layers and a drain layer of the drain layers, and a vertical stack of discrete memory material portions laterally surrounding the vertical word line.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YASSER ABDELAZIEZ whose telephone number is (571)270-5783. The examiner can normally be reached Monday - Friday 9 am - 6 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ajay Ojha can be reached at (571) 272-8936. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YASSER A ABDELAZIEZ, PhD/Primary Examiner, Art Unit 2898