Prosecution Insights
Last updated: July 17, 2026
Application No. 18/176,113

SILICON CARBIDE SEMICONDUCTOR DEVICE

Non-Final OA §102
Filed
Feb 28, 2023
Priority
Mar 22, 2022 — JP 2022-044876
Examiner
MAI, ANH D
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Fuji Electric Co., Ltd.
OA Round
1 (Non-Final)
38%
Grant Probability
At Risk
1-2
OA Rounds
3m
Est. Remaining
48%
With Interview

Examiner Intelligence

Grants only 38% of cases
38%
Career Allowance Rate
265 granted / 701 resolved
-30.2% vs TC avg
Moderate +10% lift
Without
With
+9.9%
Interview Lift
resolved cases with interview
Typical timeline
3y 8m
Avg Prosecution
36 currently pending
Career history
760
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
82.8%
+42.8% vs TC avg
§102
11.6%
-28.4% vs TC avg
§112
5.0%
-35.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 701 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Status of the Claims Applicant’s election without traverse of Group I and Species 2, as shown in FIG. 3, in the reply filed on March 30, 2026 is acknowledged. Applicant identifies claims 1-6 are readable on the Elected Group I, and Species 2. Non-elected Inventions and/or Species, claims 7-21 have been withdrawn from consideration. Claims 1-21 are pending. Action on merits of the Elected Invention and Species, claims 1-6 follows. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) submitted on February 28, 2023 and July 30, 2025 have been considered by the examiner. Specification The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: VDMOS SILICON CARBIDE SEMICONDUCTOR DEVICE WITH PARALLEL PN LAYER UNDER DEVICE STRUCTURES HAVING AMOUNT OF A SECOND-CONDUCTIVITY-TYPE CHARGE DECREASING FROM TOP SURFACE TO BOTTOM SURFACE Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by SAITO et al. (US. Patent No. 6,888,195). With respect to claim 1, SAITO teaches a silicon carbide semiconductor device, as claimed including: a semiconductor substrate containing silicon carbide, the semiconductor substrate having a first main surface (Top, T) and a second main surface (Bottom, B) that are opposite to each other; a parallel pn layer (3/4) provided in the semiconductor substrate, the parallel pn layer (3/4) having therein a plurality of first-conductivity-type regions (3) and a plurality of second-conductivity-type regions (4) disposed adjacent to one another so as to repeatedly alternate with one another in a direction that is parallel to the first main surface (T) of the semiconductor substrate; a device structure provided between the first main surface (T) and the parallel pn layer (3/4); a first electrode (7) provided on the first main surface (T) and electrically connected to the device structure; and a second electrode (1) provided on the second main surface (B) of the semiconductor substrate, wherein the parallel pn layer (3/4) has a standard portion (Middle, M), a first portion (1) and a second portion (2), the standard portion (M) being located at a standard depth that is a center of the parallel pn layer (3/4) in a depth direction (Z) or having a range of depth, a center of the range of depth being located at the standard depth, the first portion (1) being located closer to the first main surface (T) than is the standard portion (M), the second portion (2) being located closer to the second main surface (B) than is the standard portion (M), between each adjacent two regions that includes one first-conductivity-type region (3) and one second-conductivity-type region (4) of the parallel pn layer (3/4) that are adjacent to each other, in the standard portion (M), an amount of a first-conductivity-type charge (QNM) and an amount of a second-conductivity-type charge (QPM) meet a standard condition, in the first portion (1), an amount of the second-conductivity-type charge (QP1) is greater than (>) an amount of the first-conductivity-type charge (QN1), is greater than (>) an (sic) amount of the second-conductivity-type charge (QPM) in the standard portion, and continuously increases with a first gradient in a first direction (up) that is the depth direction from the standard portion (M) toward the first main surface (T), in the second portion (2), an amount of the first-conductivity-type charge (QN2) is greater than (>) the amount of the second-conductivity-type charge (QP2), an amount of the second-conductivity-type charge (QP2) is less than (<) the amount of the second-conductivity-type charge (QPM) of the standard portion (M), and continuously decreases with a second gradient in a second direction (down) that is the depth direction from the standard portion (M) toward the second main surface (B). (See FIGs. 1A-B). With respect to claim 2, an absolute value of the first gradient of SAITO is greater than an absolute value of the second gradient. With respect to claim 3, an equation “CB=(Qp-Qn/Qn)×100” is satisfied in the parallel pn layer (3/4), where, “Qp=Na×Wp” and “Qn=Nd×Wn”, “Na” and “Wp” respectively represent a carrier concentration and a width of the one first-conductivity-type region included in said each adjacent two regions, and “Nd” and “Wn” respectively represent a carrier concentration and a width of the one second-conductivity-type region included in said each adjacent two regions, the CB has an upper limit of +160% in the first portion and a lower limit of -30% in the second portion. With respect to claim 4, an equation “CB=(Qp-Qn/Qn)×100” and an expression “5≤ | CB1+/CB1- | ≤6” of SAITO are satisfied in the parallel pn layer (3/4), where, “Qp=Na×Wp” and “Qn=Nd×Wn”, “Na” and “Wp” respectively represent a carrier concentration and a width of the one first-conductivity-type region included in said each adjacent two regions, and “Nd” and “Wn” respectively represent a carrier concentration and a width of the one second-conductivity-type region included in said each adjacent two regions, “CB1+” corresponds to a CB at a first depth located at a first distance in the first direction away from the standard depth, “CB1-” corresponds to a CB at a second depth located at a second distance in the second direction away from the standard depth, and the first and second distances are the same distance. With respect to claim 5, the standard condition of SAITO defines amounts of the first-conductivity-type charge (QN) and the second-conductivity-type charge (QP) in each adjacent two regions that obtain a greatest breakdown voltage. With respect to claim 6, an impurity concentration of the plurality of first-conductivity-type regions (3) of SAITO is constant in the depth direction. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANH D MAI whose telephone number is (571)272-1710 (Anh.Mai2@uspto.gov). The examiner can normally be reached 10:00-4:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue A Purvis can be reached at 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ANH D MAI/Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Feb 28, 2023
Application Filed
Jun 17, 2026
Non-Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
38%
Grant Probability
48%
With Interview (+9.9%)
3y 8m (~3m remaining)
Median Time to Grant
Low
PTA Risk
Based on 701 resolved cases by this examiner. Grant probability derived from career allowance rate.

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