DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Applicant’s election without traverse of Group I, Species 1 in the reply filed on April 03, 2026 is acknowledged.
Applicant identified Claims 1-3 and 5 are readable on the elected Invention and/or Species. Non-elected Invention and/or Species, Claims 4, and 6-8 have been withdrawn from consideration. Claims 1 and 7 have been amended. Claims 1-8 are pending.
Action on merits of the Elected Invention, Group I, Species 1, claims 1-3 and 5 follows.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on February 28, 2023 and August 25, 2025 have been considered by the examiner.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
A SILCION CARBIDE SEMICONDUCTOR DEVICE HAVING A VOLTAGE WITHSTANDING STRUCTURE OF SECOND CONDUCTIVITY TYPE OVERLAPPING A SECOND PARALLEL PN LAYER FORMED IN TERMINATION REGION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 and 5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KAWADA (US. Pub. No. 2021/0167) of record.
With respect to claim 1, KAWADA teaches a silicon carbide semiconductor device, as claimed including:
a semiconductor substrate () containing silicon carbide, the semiconductor substrate having a first main surface (40) and a second main surface that are opposite to each other, the semiconductor substrate further having an active region (10) and a termination region (30) surrounding a periphery (20) of the active region;
a first parallel pn layer (67/68) in which a plurality of first first-conductivity-type regions (67) and a plurality of first second-conductivity-type regions (68) are disposed so as to repeatedly alternate with one another in a direction (X) parallel to the first main surface of the semiconductor substrate, the first parallel pn layer being provided in the semiconductor substrate, in the active region (10);
a second parallel pn layer (67/68) in which a plurality of second first-conductivity-type regions (67) and a plurality of second second-conductivity-type regions (68) are disposed so as to repeatedly alternate with one another in the direction (X), the second parallel pn layer being provided in the semiconductor substrate, in the termination region (30);
a device structure provided between the first main surface (40) of the semiconductor substrate and the first parallel pn layer (67/68), in the active region (10);
a first electrode (15) provided on the first main surface (40) of the semiconductor substrate, the first electrode being electrically connected to the device structure;
a second electrode (16) provided on the second main surface of the semiconductor substrate; and
a first semiconductor region (34) of the second conductivity type configuring a voltage withstanding structure and being electrically connected to the first electrode (15), the first semiconductor region (34) being selectively provided between the first main surface (40) of the semiconductor substrate and the second parallel pn layer in the termination region (30), the first semiconductor region (34) surrounding the periphery of the active region (10),
wherein the first semiconductor region (34) has an overlap area where the first semiconductor region (34) and one of the plurality of second second-conductivity-type regions (68) overlap each other in a plan view of the silicon carbide semiconductor device,
in the overlap area, or
the first semiconductor region (34) and the one of the plurality of second second-conductivity-type regions (68) are in contact with each other in a thickness direction, or
between the first semiconductor region and the one of the plurality of second second-conductivity-type regions in the thickness direction, an other second-conductivity-type region is provided and has a thickness of at most 0.1 µm. (See FIG. 2).
With respect to claim 2, the overlap area of KAWADA is provided in plurality, and respective ones of the plurality of second second-conductivity-type regions (68) are in contact with the first semiconductor region (34) without the other second-conductivity-type region intervening therebetween.
With respect to claim 5, the silicon carbide semiconductor device of KAWADA further comprises in the first semiconductor region (34), a spatial modulation region in which an impurity concentration distribution of the first semiconductor region (34) decreases in a direction from the active region (10) to the termination region (30).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over KAWADA ‘167 as applied to claim 1 above, and further in view of KOBAYASHI et al. (US. Pub. No. 2018/0040690).
KAWADA teaches the silicon carbide semiconductor device as described in claim 1 above including: a second semiconductor region (11) of the second conductivity type, provided on the first parallel pn layer (67/68) in the active region (10), the second semiconductor region (11) having a first surface and a second surface opposite to each other, the second surface facing the first parallel pn layer (67/68),
wherein the first semiconductor region (34) has a first surface and a second surface opposite to each other, the second surface facing the second parallel pn layer (67/68).
Thus, KAWADA is shown to teach all the features of the claim with the exception of explicitly disclosing the first surface of the first semiconductor region being closer to the first electrode than is the first surface of the second semiconductor region.
However, KOBAYSAHI teaches a silicon carbide semiconductor device including:
a second semiconductor region (3a) of a second conductivity type provided in active region (1102), the second semiconductor region (3a) having a first surface and a second surface opposite to each other, the second surface facing the drift layer (1),
wherein first semiconductor region (6/7) has a first surface and a second surface opposite to each other, the second surface facing the drift layer (1), the first surface of the first semiconductor region (6/7) being closer to the first electrode (22) than is the first surface of the second semiconductor region (3a). (See FIGs. 5, 7, 9).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the first semiconductor region of KAWADA having the first surface that is closer to the first electrode than the first surface of the second semiconductor region as taught by KOBAYASHI so that various types of structure may be implemented.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANH D MAI whose telephone number is (571)272-1710 (Email: Anh.Mai2@uspto.gov) The examiner can normally be reached 10:00-4:00PM.
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/ANH D MAI/Primary Examiner, Art Unit 2893
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