Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
The following is a non-final office action in response to the communication filed 2/28/2023.
Claims 1-20 are currently pending.
Claims 17-20 have been withdrawn.
Claims 1-16 have been examined.
Priority
Acknowledgment is made of applicant's claim for foreign priority based under 35 U.S.C.§119 on an application filed in Korean Patent Application No. 10-2022-0087109, filed on July 14, 2022, in the Korean Intellectual Property Office. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Election/Restriction
Applicant's election without traverse of claims 1-16 in Group I, in the reply filed on 9/5/2025, is acknowledged. Claims 17-20 directed to nonelected Group II are withdrawn from further consideration pursuant to 37 CFR 1.142(b), there being no allowable generic or linking claim. Election was made without traverse in the same reply.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 2/28/2023, are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered by the examiner.
The second IDS submitted on 2/28/2023 appears to have been duplicated in the submission as both have the same references, both have been considered herein. Applicant is requested to verify if this duplication was an unintentional duplication or if a different IDS with different references was intended to be submitted.
Specification
TITLE OF THE INVENTION
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Semiconductor Device with Active Layers Doped by Sacrificial Layers and Method Thereof
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
The following annotated Figure will be used in discussion:
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Claims 11 and 13-15 are rejected under 35 U.S.C. 102 (a)(2) as being anticipated by Chang et al. US 20220359768 A1.
Regarding claim 11:
A semiconductor device (Chang, [0019], GAAFET device) comprising:
a substrate (Fig. 9A-9C, substrate 102) including an active pattern; (superlattice 155)
a channel pattern (Fig. 4Cnanostructure layers 121) on the active pattern,(See Fig. 4C) the channel pattern including a plurality of semiconductor patterns spaced apart from each other and vertically stacked; (Fig. 4C, nanostructure layers 121 is spaced apart in fins 120a and 120b and vertically stacked over nanostructure layers 122)
a source/drain pattern (Fig. 7C, source/drain regions 170) connected to the plurality of semiconductor patterns (Fig. 7C channels 110); and
a gate electrode (annotated Fig. 8B, GAA structure 158 including 158_1 and 158_2) on the plurality of semiconductor patterns, the gate electrode including a first inner electrode (gate electrode 158_1) provided below a first semiconductor pattern (Annotated Fig.8A, the gate electrode 158_1 is below a channel 610_1 which includes 610_1p1, 610_1p2, and 610_1p3) among the plurality of semiconductor patterns (Annotated Fig. 8A, there is a plurality of nanostructure channels 610 including 610_1 and 610_2), and a second inner electrode (Fig. 8B, gate electrode 158_2) provided above the first semiconductor pattern, (Annotated Fig. 8A, 158_2 is above a channel 610) wherein the first semiconductor pattern (the channel 610) includes a first portion adjacent to the first inner electrode,(annotated Fig. 8A, 610p1 is adjacent to the gate electrode 158_1) a second portion adjacent to the second inner electrode, (annotated Fig. 8A, 610_1p2 is adjacent to the gate electrode 158_2) and a third portion between the first portion and the second portion, (annotated Fig. 8A, 610_1p3 is between 610_1p1 and 610_1p2) wherein the first semiconductor pattern includes a dopant having an atomic weight greater than an atomic weight of silicon (Si), and ([0050], the nanostructure layers 121 which can be the channel layers can be dopped with phosphorous which has a higher atomic weight (30.97 u) than silicon (28.09 u))
wherein a dopant concentration of the third portion is smaller than a dopant concentration of each of the first and second portions. ([0038], the channels 610 are surface dopped, where the dopant concentration in 610p1 and 610p2 would be 1×1015 atoms/cm3, and the middle/third portion 610p3 is less 1×1012 atoms/cm3
Regarding claim 13, Chang further discloses:
wherein the dopant includes at least one of phosphorous (P), arsenic (As), antimony (Sb), bismuth (Bi), sulfur (S), selenium (Se), tellurium (Te), gallium (Ga) and indium (In). (Chang, [0051], For NFET the channel doping is phosphorous P. See also Fig. 10.)
Regarding claim 14, Chang further discloses:
wherein the third portion includes undoped silicon (undoped Si). ([0030], the superlattice is made with Si.)
Regarding claim 15, Chang further discloses:
wherein a dopant concentration of an uppermost second semiconductor pattern among the plurality of semiconductor patterns decreases toward an upper portion of the uppermost second semiconductor pattern. (Annotated Fig. 8A, channel 610_2 is the uppermost semiconductor pattern and has a decreased dopant amount towards the upper portion of the pattern.)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Chang as applied to claim 11 above, and further in view of Ko et al. US 20230065708 A1 (hereinafter Ko).
Regarding claim 12, Chang discloses all of the elements of claim 11.
Chang does not appear to disclose, “wherein a dopant concentration of each of the first and second portions is 1.0x1017 atoms/cm3 to 1.0x1018 atoms/cm3.”
Ko which teaches a semiconductor GAA FET device (Ko, [0012]), discloses:
wherein a dopant concentration of each of the first and second portions(annotated Fig. 8A, first and second portions 610_1p1 and 610_1p2) is 1.0x1017 atoms/cm3 to 1.0x1018 atoms/cm3. ([0019], semiconductor layer 124 which can be epitaxially grown silicon (Si) can have a dopant concentration between 1.0 atoms/cm3 to about 1×10.sup.18 atoms/cm3.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Chang to have wherein a dopant concentration of each of the first and second portions is 1.0x1017 atoms/cm3 to 1.0x1018 atoms/cm3 as taught by Ko for purposes of providing differing oxidation and/or etching selectivity properties. (Ko, [0019].)
Claim 16 is rejected under 35 U.S.C. 103 as obvious over Chang in view of Liaw US 20210098627 A1 (hereinafter Liaw).
Regarding claim 16, Chang discloses all the elements of claim 11.
Chang does not appear to disclose:
wherein the semiconductor patterns include the first semiconductor pattern with a first width in a first direction and a second semiconductor pattern with a second width in the first direction, the second semiconductor pattern being lower than the first semiconductor pattern, the second width being greater than the first width.
Liaw, which teaches an integrated IC device with GAAFET devices (Liaw, Abstract), discloses:
wherein the semiconductor patterns (Fig. 9B, semiconductor layer 220A top layer and middle layer) include the first semiconductor pattern (semiconductor layer 220A top layer) with a first width (Fig. 9B, distance D3 which defines the channel width of the top layer) in a first direction and a second semiconductor pattern (Fig. 9B, semiconductor 220A middle layer) with a second width (Fig. 9B, distance D2 which defines the channel width of the middle layer) in the first direction, the second semiconductor pattern being lower than the first semiconductor pattern, the second width being greater than the first width. (D3 is wider than D2 which results in the channel width of the middle layer being wider than the top layer.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Chang to have the semiconductor patterns include the first semiconductor pattern with a first width in a first direction and a second semiconductor pattern with a second width in the first direction, the second semiconductor pattern being lower than the first semiconductor pattern, the second width being greater than the first width as taught by Liaw for purposes of having a tapered profile for the trench that makes the source/drain feature. The tapered profile causes the epitaxial growth process to be a bottom-up conformal epitaxial growth process preventing voids. (Liaw, [0035])
Claims 1, 2, and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. US 20220359768 A1 (hereinafter Chang) in view of Moriwaki US 20220093613 A1 (hereinafter Moriwaki) in further view of Glass et al. US 20190221649 A1 (hereinafter Glass).
Regarding Claim 1, Chang discloses:
A semiconductor device (Chang, [0019], GAAFET device) comprising:
a substrate (Fig. 9A-9C, substrate 102) including …;
an active pattern (superlattice 155) on the active region (a working device is considered by default to be in the active region) ….;
a channel pattern(Fig. 4C nanostructure layers 121 which becomes channel 610 in Fig. 6D) and a source/drain pattern (Fig. 7C, source/drain regions 170) on the active pattern, the channel pattern including a plurality of semiconductor patterns spaced apart from each other and vertically stacked; (Fig. 4C, nanostructure layers 121 is spaced apart in fins 120a and 120b and vertically stacked over nanostructure layers 122)
….
a gate electrode (Fig. 8B, GAA structure 158 including 158_1 and 158_2) on the plurality of semiconductor patterns, the gate electrode including an inner electrode (gate electrode 158_1) provided interposed between adjacent semiconductor patterns among the plurality of semiconductor patterns (Fig. 8B, , GAA structure 158 is between channels 610 that were originally nanostructured layers 121), wherein each of the plurality of dummy sacrificial layers includes a dopant having an atomic weight greater than an atomic weight of each of silicon-germanium (SiGe) and silicon (Si), and ([0050], the nanostructure layers 122 which can be the channel layers can be dopped with phosphorous which has a higher atomic weight (30.97 u) than silicon (28.09 u))
wherein a concentration of the dopant is 1.0x1019 atoms/cm3 to 1.0x1021 atoms/cm3. ([0032] the dopant concentration in doped nanostructured layers 122 thus formed can be between about 1×1012 atoms/cm3and about 1×1020 atoms/cm3.)
Chang further teaches:
the … stacked pattern (Fig. 4C, having two fins 151 made of GAAFETs 120a and 120b) …, and the … stacked pattern including a plurality of … sacrificial layers(nanostructured layer 122 SiGe doped layers) and a plurality of … layers (nanostructure layer 121 Si doped layers), wherein the plurality of … sacrificial layers and the … of dummy layers are alternately stacked; (Fig. 4C, nanostructures layer 121 and 122 are alternately stacked) and …
Chang does not specifically disclose:
… an active region and a dummy region;
… and a dummy pattern on the dummy region;
Moriwaki which teaches, manufacturing of semiconductor device with three dimensional transistor (i.e. transistors with nanowires) in a SRAM (Moriwaki, [0009]), discloses:
A semiconductor device (Fig. 1A including transistors N1-N5 and transistors N21-24) comprising:
a substrate including an active region and a dummy region; ([0099], transistors N21-N24 are dummy transistors therefor implying a separate active region from the dummy region where the dummy transistors are.)
…. and a dummy pattern on the dummy region; ([0099] N21-N24 by necessity have a pattern for the devices in the dummy region.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Chang to have a dummy region with a dummy pattern on the dummy region as taught by Moriwaki for purposes of reducing manufacturing variations, improve yield and improve reliability. (Moriwaki, [0099].)
However, Moriwaki does not specifically teach that the dummy pattern has a dummy stacked pattern or “the dummy stacked pattern horizontally spaced apart from the channel pattern and the source/drain pattern, and the dummy stacked pattern including a plurality of dummy sacrificial layers and a plurality of dummy layers, wherein the plurality of dummy sacrificial layers and the plurality of dummy layers are alternately stacked.”
Glass, teaches that non-active regions do not need to be replaced and therefore may have the sacrificial material that was used in previous formation steps remaining in these non-active areas. (Glass, [0063].) Therefore, Glass teaches that there is a non-active region that has devices that are non-functional dummy devices with a dummy stack pattern including the sacrificial layers that were part of the formation of the active pattern. Chang which teaches the active pattern as explained above may be used as to explain the material of the dummy stacked pattern that would be spaced apart from the channel pattern and source/drain patterns that are in the active area. This pattern would be repeated in the non-active area and the sacrificial layers would still be present as the dummy layers in the dummy stacked pattern.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Chang and Moriwaki to have the dummy stacked pattern in non-active areas as taught Glass, (Glass, [0063]) such that to ensure more predictable results in manufacturing by repeating the active pattern both in active and non-active areas in earlier processing steps there is better yield. This would lead to a predictable result of patterning non-active devices that are in the unused portion of the final IC. (Glass, [0063].)
Regarding claim 2, Chang, Moriwaki, and Glass teaches all the elements of claim 1.
Chang further discloses:
wherein the dopant includes at least one of phosphorous (P), arsenic (As), antimony (Sb), bismuth (Bi), sulfur (S), selenium (Se), tellurium (Te), gallium (Ga) and indium (In). (Chang, [0051], For NFET the channel doping is phosphorous P. See also Fig. 10.)
Regarding claim 4, Chang, Moriwaki, and Glass teaches all the elements of claim 1.
Chang further discloses:
wherein each of the plurality of dummy layers includes undoped silicon (undoped Si). (Chang, [0030], the superlattice is made with Si.)
Claim 3 rejected under 35 U.S.C. 103 as being unpatentable over Chang, Moriwaki, and Glass as applied to claim 1 above, and further in view of Young et al. US 20210202697 A1 (hereinafter Young).
Regarding claim 3, Chang, Moriwaki, and Glass disclose the semiconductor device of claim 1.
Chang, Moriwaki, and Glass appear to be silent regarding the “a concentration of germanium (Ge) in each of the plurality of dummy sacrificial layers is 5at% to 40at%.”
However Young, which teaches a GAA device where the channel regions have different atomic concentrations so an element germanium (Young, [0010]), discloses:
a concentration of germanium (Ge) in each of the plurality of dummy sacrificial layers is 5at% to 40at%. (Young, [0019], the atomic concentration of germanium (GE) can range from 20% to 40% in semiconductor layer 52 which is the sacrificial layer.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Chang, Moriwaki, and Glass to have a concentration of germanium (Ge) in each of the plurality of dummy sacrificial layers is 5at% to 40at% as taught by Young for purposes of providing differing etching selectivity properties. (Young, [0019].)
Claims 6 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Chang, Moriwaki, and Glass as applied to claim 1 above, and further in view of Tsai et al. US 20210328012 A1 (hereinafter Tsai).
Regarding claim 6, Chang, Moriwaki, and Glass disclose the semiconductor device of claim 1.
Chang discloses:
the dummy stacked pattern (Fig. 4C, having two fins 151 made of GAAFETs 120a and 120b) includes the plurality of dummy sacrificial layers (nanostructured layer 122 SiGe doped layers) stacked vertically and overlapping(Fig. 4C, nanostructures layer 121 and 122 are stacked vertically and overlapping) with the plurality of dummy layers, (nanostructure layer 121 Si doped layers), and
Tsai, which teaches the fabrication of GAA FET structures (Tsai, Background), discloses:
the dummy stacked pattern includes a silicon-germanium-dopant layer interposed between silicon-germanium (SiGe) layers. (Fig. 20 and [0094], sacrificial layer 414 are doped silicon-germanium and layers 413 and 415 is un-doped silicon-germanium. This creates a dummy stacked pattern with the dopant with the doped silicon-germanium between the two heavily doped regions.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Chang, Moriwaki, and Glass to have the dummy stacked pattern includes a silicon-germanium-dopant layer interposed between silicon-germanium (SiGe) layers as taught by Tsai for purposes of having improved tensile strain in the undoped layers result from the doped layers. (Tsai, [0091].)
Regarding claim 8, Chang, Moriwaki, and Glass disclose the semiconductor device of claim 1.
Chang discloses:
the dummy stacked pattern (Fig. 4C, having two fins 151 made of GAAFETs 120a and 120b) includes the plurality of dummy sacrificial layers (nanostructured layer 122 SiGe doped layers) stacked vertically and overlapping(Fig. 4C, nanostructures layer 121 and 122 are stacked vertically and overlapping) with the plurality of dummy layers, (nanostructure layer 121 Si doped layers), and
Change does not appear to teach:
wherein the dummy stacked pattern includes a silicon-germanium-dopant layer and a silicon-germanium layer which are alternately stacked.
Tsai, which teaches the fabrication of GAA FET structures (Tsai, Background), discloses:
wherein the dummy stacked pattern includes a silicon-germanium-dopant layer and a silicon-germanium layer which are alternately stacked. (Fig. 20 and [0085], sacrificial layer 412 and 414 are doped silicon-germanium and layers 413 and 415 is un-doped silicon-germanium. This creates a dummy stacked pattern with the dopant with the doped silicon-germanium between the two heavily doped regions.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Chang, Moriwaki, and Glass to have the dummy stacked pattern includes a silicon-germanium-dopant layer and a silicon-germanium layer which are alternately stacked as taught by Tsai for purposes of having improved tensile strain in the undoped layers result from the doped layers. (Tsai, [0091].)
Claims 7 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Chang, Moriwaki, Glass and Tsai as applied to claims 6 and 8 above, and further in view of Guha et al. US 20200044087 A1 (hereinafter Guha.)
Regarding claim 7, Chang, Moriwaki, Glass and Tsai teach the semiconductor device of claim 6.
Chang, Moriwaki, Glass and Tsai do not appear to teach wherein the silicon-germanium-dopant layer does not include silicon-germanium-carbon (SiGeC).
Guha, which teaches, Sub-fin isolation schemes for gate-all-around (GAA) transistor devices (Guha, Abstract), discloses:
the silicon-germanium-dopant layer does not include silicon-germanium-carbon (SiGeC). ( [0033], adding carbon would prevent diffusion acting as diffusion barrier and preventing dopant diffusion from one layer to the other.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Chang, Moriwaki, Glass and Tsai to have not to include carbon/silicon-germanium-carbon in the silicon-germanium dopant layer because as taught by Guha including carbon would have the purpose of preventing dopant diffusion. (Guha, [0033])
Regarding Claim9 Chang, Moriwaki, Glass and Tsai teach the semiconductor device of claim 8.
Chang, Moriwaki, Glass and Tsai do not appear to teach wherein the silicon-germanium-dopant layer does not include silicon-germanium-carbon (SiGeC).
Guha, which teaches, Sub-fin isolation schemes for gate-all-around (GAA) transistor devices (Guha, Abstract), discloses:
the silicon-germanium-dopant layer does not include silicon-germanium-carbon (SiGeC). ( [0033], adding carbon would prevent diffusion acting as diffusion barrier and preventing dopant diffusion from one layer to the other.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Chang, Moriwaki, Glass and Tsai to have not to include carbon/silicon-germanium-carbon in the silicon-germanium dopant layer because as taught by Guha including carbon would have the purpose of preventing dopant diffusion. (Guha, [0033])
Claim 10 rejected under 35 U.S.C. 103 as being unpatentable over Chang, Moriwaki, and Glass as applied to claim1 above, and further in view of Ha et al. US CN113130629A (Where US 20210217860 A1 is provided as a translation and hereinafter Ha).
Regarding claim 10, Chang, Moriwaki, and Glass teach all the elements of semiconductor device of claim 1.
Chang further discloses:
wherein the gate electrode (GAA structures 158) further includes a portion interposed between adjacent semiconductor patterns among the plurality of semiconductor patterns (Fig. 8A and 8Bat least the portions defined by the gate dielectric layer 160, the work function metal layer 162 and gate electrode 163 are between the channel regions 610), and
the semiconductor device further comprising a gate insulating layer between the adjacent semiconductor patterns and the portion of the gate electrode (gate dielectric 160-161), an inner spacer (inner spacer 164) between the gate insulating layer and the source/drain pattern; (Fig. 8A and 8B, the inner spacer 164 is between the gate dielectric 160-161 and the source/drain region 170)
a gate spacer on a sidewall of the gate electrode, (sidewall spacer 128) a gate capping pattern on a top surface of the gate electrode (gate structure 108), a sacrificial pattern on an uppermost dummy layer among the plurality of dummy layers, (Fig. 6D sacrificial structure 107) a mask pattern on the sacrificial pattern, an interlayer insulating layer on the gate capping pattern and the mask pattern, (Fig. 6C, [0034], sacrificial structure 107 and sidewall spacer 128 create a mask pattern)
Chang does not appear to directly disclose:
an active contact electrically connected to the source/drain pattern through the interlayer insulating layer, a metal-semiconductor compound layer interposed between the active contact and the source/drain pattern, a gate contact passing through the interlayer insulating layer and the gate capping pattern to be electrically connected to the gate electrode,
a first metal layer on the interlayer insulating layer, the first metal layer including a power wiring and first wirings electrically connected to the active contact and the gate contact, respectively, and
a second metal layer on the first metal layer, the second metal layer including second wirings electrically connected to the first metal layer.
Ha, which teaches a semiconductor device including with vertically stacked channel pattern (Ha, [0006]), discloses:
an active contact (Fig. 1 and 2, active contact AC) electrically connected to the source/drain pattern through the interlayer insulating layer, (Fig.2, [0041] active contact AC electrically connected to source/drain SD1 and SD2) a metal-semiconductor compound layer interposed between the active contact and the source/drain pattern, ([0041], the silicide pattern which is between the active contact AC and the source/drain pattern SD1 which is made from a metal silicon material) gate contact (Fig. 30, gate contact GC) passing through the interlayer insulating layer (insulating layer 120) and the gate capping pattern (gate capping pattern GP) to be electrically connected to the gate electrode, ([0042] GC includes a conductive pattern therefor is conductive and electrically conductive to the gate electrode GE)
a first metal layer (Fig. 2 and Fig. 30 via VI) on the interlayer insulating layer, (insulating layer 120) the first metal layer including a power wiring and first wirings electrically connected to the active contact and the gate contact, respectively, and (Fig. 2 and 30, [0044], The second interconnection line may be electrically connected to the gate contact GC through the via VI.)
a second metal layer (interconnect lines IL) on the first metal layer, the second metal layer including second wirings electrically connected to the first metal layer. (Fig. 2 and Fig. 30, first interconnection layer may include a plurality of interconnection lines IL and a plurality of vias VI.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Chang, Moriwaki, and Glass to have and active contact electrically connected to the source/drain pattern as further defined above as taught by Ha for purposes of having electrically connected active contacts (AC). (Ha, [0039].)
Allowable Subject Matter
Claim 5 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 5, the cited prior art of record does not teach or fairly suggest, along with the other claimed features, a semiconductor device comprising the dopant concentration is be 1.0x1012 atoms/cm3 to 1.0x1015 atoms/cm3.
Chang, Moriwaki, and Glass discloses all the elements of claim 1.
Chang discloses:
wherein the plurality of dummy layers include the dopant diffused from the plurality of dummy sacrificial layers, and ([0038] the nanostructure layers because surface-doped channels 610 because by an annealing process that diffuse dopants from the nanostructured layers 122.)
Chang does not disclose where the dopant concentration is be 1.0x1012 atoms/cm3 to 1.0x1015 atoms/cm3 for the channel 610. Chang does not appear to specifically disclose “a concentration of the diffused dopant is 1.0x1017 atoms/cm3 to 1.0x1018 atoms/cm3,” and does not provide motivation for increasing dopant concentration by the amount to a higher dopant concentration.
Conclusion
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/HEIM KIRIN GREWAL/Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812