Prosecution Insights
Last updated: May 29, 2026
Application No. 18/176,393

SYSTEMS AND METHODS FOR PACKAGING A SEMICONDUCTOR DEVICE

Non-Final OA §102§103
Filed
Feb 28, 2023
Examiner
PHAM, LONG
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Advanced Micro Devices, Inc.
OA Round
1 (Non-Final)
92%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 92% — above average
92%
Career Allowance Rate
1509 granted / 1649 resolved
+23.5% vs TC avg
Moderate +6% lift
Without
With
+5.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
27 currently pending
Career history
1679
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
56.9%
+16.9% vs TC avg
§102
23.7%
-16.3% vs TC avg
§112
9.5%
-30.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1649 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of claims 1-4, 7-12, and 14 in the reply filed on 11/26/25 is acknowledged. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 2, 3, 4, and 7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Agarwal et al. (US pat 10930621). With respect to claim 1, Agarwal et al. teach a semiconductor device, comprising (see figs. 1-22, particularly fig. 1 and associated text): a plurality of stacked circuit dies 20, 25, 30, 40; a mold compound 130 introduced into a top tier 40 of the plurality of stacked circuit dies; and a carrier-less enclosure 110, 130, 115 attached to the top tier of the plurality of stacked circuit dies. With respect to claim 2, Agarwal et al. teach the plurality of stacked circuit dies includes at least one lower tier 20, 25, 30, 35 of one or more additional circuit dies. See fig. 1 and associated text. With respect to claim 3, Agarwal et al. teach an additional mold compound 90, 95, 100, 105 introduced into the at least one lower tier of the plurality of stacked circuit dies, wherein the additional mold compound is different from the mold compound introduced into the top tier of the plurality of stacked circuit dies. See fig. 1 and associated text. With respect to claim 4, Agarwal et al. teach the carrier-less enclosure includes a heat spreader 110, 115 attached to one or more circuit dies included in the top tier of the plurality of stacked circuit dies. See fig. 1 and associated text. With respect to claim 7, Agarwal et al. teach the heat spreader is continuous vertically (left 110). See fig. 1 and associated text. Claim(s) 1, 2, 3, 4, 8, 10, and 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by OH et al. (US pub 20130154074). With respect to claim 1, OH et al. teach a semiconductor device, comprising (see figs. 1-15, particularly fig. 11 and associated text): a plurality of stacked circuit dies 400,600; a mold compound 510 introduced into a top tier 40 of the plurality of stacked circuit dies; and a carrier-less enclosure 510,530 attached to the top tier of the plurality of stacked circuit dies. With respect to claim 2, OH et al. teach the plurality of stacked circuit dies includes at least one lower tier 600 of one or more additional circuit dies. See fig. 11 and associated text. With respect to claim 3, OH et al. teach an additional mold compound 530 introduced into the at least one lower tier of the plurality of stacked circuit dies, wherein the additional mold compound is different from the mold compound introduced into the top tier of the plurality of stacked circuit dies. See fig. 11 and associated text. With respect to claim 8, OH et al. teach the carrier-less enclosure includes an extension of the mold compound (lateral part of 510) above one or more circuit dies included in the top tier of the plurality of stacked circuit dies. See fig. 11 and associated text. With respect to claim 10, OH et al. teach the mold compound comprises a non-dielectric insulator 510 introduced between one or more circuit dies (left and right 400) included in the top tier of the plurality of stacked circuit dies. See fig. 11 and associated text. With respect to claim 11, OH et al. teach the semiconductor device does not include any dielectric gap filler introduced between one or more circuit dies (right and left 400) included in the top tier of the plurality of stacked circuit dies. See fig. 11 and associated text. Claim(s) 12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Agarwal et al. (US pat 10930621). With respect to claim 12, Agarwal et al. teach a semiconductor device, comprising (see figs. 1-22, particularly fig. 1 and associated text): a mold compound 130 introduced into a top tier 40 of a plurality of stacked circuit dies 20, 25, 30, 40; and a heat spreader 110, 115 attached to one or more circuit dies included in the top tier of the plurality of stacked circuit dies, wherein the mold compound 130 and the heat spreader 110, 115 form a carrier-less enclosure of the top tier of the plurality of stacked circuit dies. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Agarwal et al. (US pat 10930621) in combination with OH et al. (US pub 20130154074). With respect to claim 14, Agarwal et al. fail to teach forming a non-dielectric insulator introduced between the one or more circuit dies included in the top tier of the plurality of stacked circuit dies. OH et al. teach a similar structure in which OH et al. teach forming a non-dielectric insulator resin introduced between the one or more circuit dies 410, 450, 470 included in the top tier of the plurality of stacked circuit dies. See fig. 11 and associated text. It would have been obvious to one of ordinary skill in the art of making semiconductor devices to incorporate the teaching of OH et al. into the device of Agarwal et al. to provide insulation for the stacked dies. See fig. 11 and associated text. Allowable Subject Matter Claim 9 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Examiner’s Cited References The cited references generally show the similar or related structure having a molded and stacked dies without a carrier or support as presently claimed by applicant. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to LONG PHAM whose telephone number is (571)272-1714. The examiner can normally be reached Mon-Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. LONG . PHAM Examiner Art Unit 2823 /LONG PHAM/Primary Examiner, Art Unit 2897
Read full office action

Prosecution Timeline

Feb 28, 2023
Application Filed
Jul 18, 2025
Response after Non-Final Action
Feb 24, 2026
Non-Final Rejection mailed — §102, §103
May 18, 2026
Applicant Interview (Telephonic)
May 18, 2026
Examiner Interview Summary

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12635524
ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THE SAME
3y 8m to grant Granted May 19, 2026
Patent 12635359
ARRAY SUBSTRATE AND DISPLAY PANEL
3y 5m to grant Granted May 19, 2026
Patent 12628692
SEMICONDUCTOR PACKAGE, SEMICONDUCTOR BONDING STRUCTURE, AND METHOD OF FABRICATING THE SAME
3y 5m to grant Granted May 12, 2026
Patent 12628694
INTEGRATED BARE DIE PACKAGE, AND RELATED FABRICATION METHODS
3y 4m to grant Granted May 12, 2026
Patent 12622317
PACKAGING ARCHITECTURE FOR MODULAR DIE INTEROPERABILITY
4y 4m to grant Granted May 05, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
92%
Grant Probability
97%
With Interview (+5.5%)
2y 3m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1649 resolved cases by this examiner. Grant probability derived from career allowance rate.

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