DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of species (a), drawn to Figs. 5A-5B in the reply filed on 10/07/2025 is acknowledged. The traversal is on the ground(s) that the embodiment of Figs. 6A-6B does not read on the claims 17-19. This is not found persuasive because the argument does not explain how the embodiment in Figs. 5A-5B is indistinguishable from the embodiment in Figs. 6A-6B.
The Examiner however agrees that the claims 17-19 read on the embodiment of Figs. 5A-5B, not the embodiment of Figs. 6A-6B. Thus, the claims 17-19 are examined together with the claims 1-16 and 20.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 7-8 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 7 recites “wherein the etching comprises etching with an infinite selectivity of the amorphous polysilicon relative to a material of the dielectric layer”. There is no disclosure of an infinite selectivity in etching of polysilicon with respect to dielectric such as oxide. In fact, the specification explicitly state that this etching is highly selective, but not infinite (see [0023] of the published specification). For the purpose of examination, it is interpreted that an “infinite selectivity” means a “high selectivity”.
Claim 8 is dependent of claim 7 and inherits the same deficiency as claim 7.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-8, 14-15, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US 2014/0252486 A1).
Regarding claim 1, Lin teaches a method (Figs. 1A-5C) of forming an integrated circuit, comprising:
first, forming a first fin (leftmost fin 112 in Fig. 1A) and a second fin (second fin 112 to the right of the leftmost fin in Fig. 1A) from a semiconductor layer (silicon layer of the substrate, as described in [0015] of Lin), with an area (area of the trench between first and second fin, as shown in Fig. 1A) between the first fin and the second fin;
second, forming a dielectric layer (118) covering at least a portion of the first fin, at least a portion of the second fin, and at least a portion of the area; and
third, forming amorphous polysilicon (120, as described in [0019] of Lin) covering a least a portion of the dielectric layer (as shown in Fig. 1A).
Regarding claim 2, Lin teaches all limitations of the method of claim 1 and also teaches wherein the area between the first fin and the second fin is a trench (trench between first and second fins and top surface of STI 114, as shown in Fig. 2A).
Regarding claim 3, Lin teaches all limitations of the method of claim 2: and also teaches wherein the at least a portion of the first fin includes a sidewall (right sidewall of leftmost fin 112) of the first fin; and wherein the at least a portion of the second fin includes a sidewall (left sidewall of the second fin) of the second fin.
Regarding claim 4, Lin teaches all limitations of the method of claim 3 and also teaches wherein the at least a portion of the area includes a bottom surface of the trench (as taught in claim 2 above).
Regarding claim 5, Lin teaches all limitations of the method of claim 4 and also teaches wherein the third step includes forming the amorphous polysilicon covering the dielectric layer in the trench in the bottom of the trench (as described in [0019] of Lin).
Regarding claim 6, Lin teaches all limitations of the method of claim 5 and further including etching the amorphous polysilicon covering the dielectric layer in the trench in the bottom of the trench (as shown in Fig. 5A-5B and described in [0032] of Lin).
Regarding claim 7, Lin teaches all limitations of the method of claim 6 and also teaches wherein the etching comprises etching with an infinite selectivity of the amorphous polysilicon relative to a material of the dielectric layer (as implied in Figs. 5A-5B of Lin, the etching of the layer 120 does not etch the dielectric layer 118).
Regarding claim 8, Lin teaches all limitations of the method of claim 7 and also teaches wherein the material includes oxide (as described in [0018] of Lin).
Regarding claim 14, Lin teaches all limitations of the method of claim 1 and further including forming a gate conductor (as described in [0032] of Lin, the layer 120 is patterned to form gate electrodes 432) from the amorphous polysilicon.
Regarding claim 15, Lin teaches all limitations of the method of claim 14 and further including forming a source region and a drain region (formation of source/drain regions are implied in the Background section of [0002]-[0004] of Lin) in the first fin, the second fin, and the area.
Regarding claim 20, Lin teaches an integrated circuit (device in Figs. 5A-5C of Lin) comprising:
a semiconductor layer (110 in Fig. 5A);
a first fin (leftmost fin 112 in Fig. 1A) and a second fin (second fin 112 to the right of the leftmost fin in Fig. 1A) extending from the semiconductor layer, with a trench (trench as shown in Fig. 5A) between the first fin and the second fin;
a gate dielectric layer (118) covering at least a portion of the first fin, at least a portion of the second fin, and at least a portion of the trench; and
an amorphous polysilicon gate (432 in Fig. 5A-5C) covering a least a portion of the gate dielectric layer.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Lin, as applied to claim 2, and further in view of Lue (US 2015/0263173 A1).
Regarding claim 9, Lin teaches all limitations of the method of claim 2 but does not teach wherein the trench has a depth distance from 0.400 µm to 6.00 µm.
Lue teaches a finFET device to be used for high voltage application that can have breakdown voltage of 30V or higher (see Abstract of Lue). The fins can have width of the order of 0.05µm, depth (distance from top of fin to top of isolation structure, as shown in Fig. 4 of Lue) of the order of 0.5 µm, and spacing between fins is about 0.4 µm (see Fig. 10).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have made the fins of Lin with dimensions as disclosed by Lue in order to have high breakdown voltage for high voltage application.
As incorporated, the depth of the trench would be 0.5 µm, which lies inside the claimed range of 0.400 µm to 6.00 µm.
Regarding claim 10, Lin teaches all limitations of the method of claim 2 but does not teach wherein the trench has a width distance from 0.150 µm to 1.500 µm.
Lue teaches a finFET device to be used for high voltage application that can have breakdown voltage of 30V or higher (see Abstract of Lue). The fins can have width of the order of 0.05µm, depth (distance from top of fin to top of isolation structure, as shown in Fig. 4 of Lue) of the order of 0.5 µm, and spacing between fins is about 0.4 µm (see Fig. 10).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have made the fins of Lin with dimensions as disclosed by Lue in order to have high breakdown voltage for high voltage application.
As incorporated, the width of the trench would be 0.4 µm, which lies inside the claimed range of 0.150 µm to 1.500 µm.
Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Lin, as applied to claim 1, and further in view of Wu et al. (US 6232208 B1).
Regarding claim 11, Lin teaches all limitations of the method of claim 1 but does not teach wherein the step of forming amorphous polysilicon includes depositing the polysilicon at a temperature of 570 °C or less.
Wu teaches a method of forming amorphous silicon layer on a substrate. Wu discloses that amorphous silicon deposited typically at temperature from 500 °C to 600 °C, and has smaller grain structures (column 4 lines 4-11 of Wu).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the amorphous silicon in the range of 500 °C to 600 °C since this is the typical temperature range for deposition of amorphous silicon.
As incorporated, since the claimed ranges of 570 °C or less "overlap or lie inside ranges disclosed by the prior art", a prima facie case of obviousness exists. Therefore, it would have been obvious at the effective filing date of the claimed invention to a person having ordinary skill in the art to have deposited the amorphous at a temperature of 570 °C or less. See In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 1469-71, 43 USPQ2d 1362, 1365-66 (Fed. Cir. 1997).
Regarding claim 12, Lin teaches all limitations of the method of claim 1 but does not teach wherein the step of forming amorphous polysilicon includes depositing the polysilicon at a temperature in a range from 520 °C to 570 °C.
Wu teaches a method of forming amorphous silicon layer on a substrate. Wu discloses that amorphous silicon deposited typically at temperature from 500 °C to 600 °C, and has smaller grain structures (column 4 lines 4-11 of Wu).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the amorphous silicon in the range of 500 °C to 600 °C since this is the typical temperature range for deposition of amorphous silicon.
As incorporated, since the claimed ranges of 570 °C or less "overlap or lie inside ranges disclosed by the prior art", a prima facie case of obviousness exists. Therefore, it would have been obvious at the effective filing date of the claimed invention to a person having ordinary skill in the art to have deposited the amorphous at a temperature of 570 °C or less. See In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 1469-71, 43 USPQ2d 1362, 1365-66 (Fed. Cir. 1997).
Regarding claim 13, Lin teaches all limitations of the method of claim 1 but does not teach wherein the step of forming amorphous polysilicon includes depositing the polysilicon at a temperature in a range from 520 °C to 550 °C.
Wu teaches a method of forming amorphous silicon layer on a substrate. Wu discloses that amorphous silicon deposited typically at temperature from 500 °C to 600 °C, and has smaller grain structures (column 4 lines 4-11 of Wu).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the amorphous silicon in the range of 500 °C to 600 °C since this is the typical temperature range for deposition of amorphous silicon.
As incorporated, since the claimed ranges of 570 °C or less "overlap or lie inside ranges disclosed by the prior art", a prima facie case of obviousness exists. Therefore, it would have been obvious at the effective filing date of the claimed invention to a person having ordinary skill in the art to have deposited the amorphous at a temperature of 570 °C or less. See In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 1469-71, 43 USPQ2d 1362, 1365-66 (Fed. Cir. 1997).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Wu, as applied to claim 15, and further in view of Shen et al. (US 2022/0059691 A1).
Regarding claim 16, Lin in view of Wu teaches all limitations of the method of claim 15 but does not teach further including forming a drift region in the first fin, the second fin, and the area.
Shen teaches a LDMOSFET on a fin (see 100A in Fig. 1A of Shen). The device includes a drift region (126), drain region (122) adjacent the drift region in the fin (110). The gate structure of the device is also formed using a replacement gate process in which the sacrificial gate is made of amorphous silicon (see [0051] and Fig. 4 of Shen).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have used Lin-Wu’s method to form the sacrificial gate layer of Shen in order to have an easier time removing the sacrificial gate (see discussion in column 4 lines 4-10 of Wu) for an LDMOSFET application.
Claims 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2007/0117364 A1) in view of Wu.
Regarding claim 17, Kim teaches a method (Figs. 9-18 of Lin) of forming an integrated circuit, comprising:
first, forming a trench (trench 240 in Fig. 14) in a semiconductor layer (201), the trench including a first (left sidewall of the trench 240) and second sidewall (right sidewall of trench 240) and a bottom surface (bottom surface of trench 240) between the first and second sidewall;
second, forming a dielectric layer (250 in Fig. 15) covering at least a portion of the first sidewall, the second sidewall, and the bottom surface (as shown in Fig. 15);
third, forming polysilicon (260, as described in [0034] of Kim) covering the dielectric layer, wherein the third step forms a bread-loafing shape in the polysilicon (as shown in Fig. 15).
But Kim does not teach that wherein the third step forms a polysilicon grain structure that inhibits passage of oxygen into the polysilicon at a location of the bread-loafing shape.
Wu teaches a method of forming amorphous silicon layer on a substrate. Wu discloses that amorphous silicon deposited typically at temperature from 500 °C to 600 °C, and has smaller grain structures (column 4 lines 4-11 of Wu).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the amorphous silicon as disclosed by Wu in order to reduce the generation of crystalline defects in the substrate (column 4 lines 12-19 of Wu).
As incorporated, the amorphous silicon layer has small grain structures (column 4 lines 4-11 of Wu). The statement “a polysilicon grain structure that inhibits passage of oxygen into the polysilicon at a location of the bread-loafing shape” is a functional language of the material in the claim. Since the material of the prior art’s method is the same material and with the same small grain structures, it would have the same properties.
Regarding claim 18, Kim in view of Wu teaches all limitations of the method of claim 17 and also teaches wherein the step of forming polysilicon includes forming amorphous polysilicon (as taught in claim 17 above).
Regarding claim 19, Kim in view of Wu teaches all limitations of the method of claim 17 and further including etching the polysilicon covering, and thereby exposing, the dielectric layer in the trench (as shown in Fig. 18 of Kim).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN A HOANG whose telephone number is (571)270-0406. The examiner can normally be reached Monday-Friday 8-9am, 10am-6pm EST.
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/Tuan A Hoang/ Primary Examiner, Art Unit 2898