Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species a (Claims 1-20 readable thereon) in the reply filed on January 16, 2026 is acknowledged.
Claim Objections
Claim 1 is objected to because of the following informalities: the phrase, “a plurality of first conductive layers are stacked via a first insulating layer one on the other in a stacking direction” is missing proper punctuation, and should read as follows: “a plurality of first conductive layers are stacked via a first insulating layer, one on the other, in a stacking direction”. Additionally, claim 1 contains the phrase, “a second stacked body in which a plurality of second conductive layers are stacked via a second insulating layer one on the other in the stacking direction,”, and with proper punctuation would read, “a second stacked body in which a plurality of second conductive layers are stacked via a second insulating layer, one on the other, in the stacking direction”. Appropriate correction is required, and the claim will be examined as such.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 6-7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tagami et al (USPGPUB 20180261575, hereinafter “Tagami”).
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Regarding Claim 1, Tagami teaches (Figs. 1, 6A-6C) a semiconductor storage device, comprising: a first chip (10); a second chip (20) bonded to (first chip 10 is seen bonded to second chip 20) the first chip (10); and a third chip (30) bonded to the second chip (20) on a side opposite (first chip 10 is bonded to the bottom side of second chip 20, and third chip 30 is seen bonded to the top side of second chip 20) the first chip (10), wherein the third chip (30) includes: a first stacked body (SB1) in which a plurality of first conductive layers (31) are stacked via a first insulating layer (Fig. 6A-6C, an insulating material 109 is seen formed mediating the conductive layers 31 in the first stacked body SB1), one on the other, in a stacking direction (z-direction), a plurality of first semiconductor films (33) each extending in the stacking direction (z-direction) in the first stacked body (SB1), a first conductive film (63b) above the first stacked body (SB1) in the stacking direction (z-direction) and extending across the first stacked body (SB1) when viewed from the stacking direction (z-direction), a second conductive film (C2) spaced from the first stacked body in a planar direction (x-direction) intersecting (z- and x- directions are seen intersecting each other) the stacking direction (z-direction), the second conductive film (C2) being at a position along the stacking direction (z-direction) that is closer to (the second conductive film c2 is lower, and therefore closer to the second chip than the first conductive film is) the second chip (20) than is the first conductive film (63b), a first plug (60b) between the first conductive film (63b) and the second conductive film (C2) in the stacking direction (z-direction) and connecting the first conductive film (63b) and the second conductive film (C2), and a first electrode (61b) at a bonding surface (BF1) of the second chip (20) and the third chip (30) and connected to (the first electrode 61b is seen connected to the second conductive film C2 by mediating contact 65b) the second conductive film (C2), the second chip (20) includes: a second stacked body (SB2) in which a plurality of second conductive layers (21) are stacked (conductive layers 21 are seen stacked in the z-direction) via a second insulating layer(Fig. 6A-6C, an insulating material 109 is seen formed mediating the conductive layers 21 in the first stacked body SB2), one on the other, in the stacking direction (z-direction), a plurality of second semiconductor films (23) each extending in the stacking direction (z-direction) in the second stacked body (SB2), a third conductive film (C3) above the second stacked body (SB2) in the stacking direction (z-direction), a fourth conductive film (C4) spaced from the second stacked body (SB2) in the planar direction (x-direction), the fourth conductive film (C4) being at a position along the stacking direction (z-direction) that is closer to the first chip (10) than is the third conductive film (C3), a second plug (60a) between the third conductive film (C3) and the fourth conductive film (C4) in the stacking direction (z-direction) and connecting the third conductive film (C3) and the fourth conductive film (C4), a second electrode (E2) at the bonding surface (BF1) of the second chip (20) and the third chip (30) and connected to (Second electrode E2 and first electrode 61b are seen connected by direct contact, and they form a conductive pathway with third conductive film C3) the first electrode (61b) and the third conductive film (C3), and a third electrode (61a) at a bonding surface (BF2) of the first chip (10) and the second chip (20) and connected to the fourth conductive film (C4), and the first chip (10) has a first wiring structure (10) therein that is connected to ([0030], “The contact plugs 53 electrically connect the electrode layers 21, 31 and 41 in the memory cell arrays stacked on the drive circuit 10 to interconnections 15 in the multi-layer interconnection 13”; wiring structure 10 acts as a driving circuit, and would be understood to be attached to the die circuitry) the third electrode (61a).
Regarding Claim 6, Tagami teaches the semiconductor storage device according to claim 1, wherein the third chip (30) has an eighth conductive film (37) connected to an end of (eighth conductive film 37 is connected to an end of first semiconductor film 31) the first semiconductor film (31), a thickness of the first conductive film (63b) is greater than (first conductive film 63b is seen having a greater thickness than that of eighth conductive film 37) a thickness of the eighth conductive film (37), the second chip (20) has a ninth conductive film (27) connected to an end of (ninth conductive film 27 is seen connected to second semiconductor film 21) the second semiconductor film (21), and a thickness of the second conductive film (C2) is greater than a thickness of (second conductive film C2 is seen having a greater thickness than that of the ninth conductive film 27) the ninth conductive film (27).
Regarding Claim 7, Tagami teaches (Figs. 1, 3) the semiconductor storage device according to claim 1, wherein the third chip (30) has a plurality of first plugs (60b), the plurality of first plugs (being a NAND memory device, see [0003], Fig. 1 of Tagami is showing a single trace of a device with a complex network of plugs, such as first plug 60b being a part of an array of different plugs, as seen in Fig. 3 of Tagami, connected in parallel) connect the first conductive film (63b) and the second conductive film (C2) in parallel, the second chip (20) has a plurality of second plugs ((being a NAND memory device, see [0003], Fig. 1 of Tagami is showing a single trace of a device with a complex network of plugs, such as second plug 60a being a part of an array of different plugs, as seen in Fig. 3 of Tagami, connected in parallel)), and the plurality of second plugs (60a) connect the third conductive film (C3) and the fourth conductive film (C4) in parallel.
Allowable Subject Matter
Claims 8-20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 8, the closest available prior art, that of Tagami, alone or in combination with any other references, fails to teach the limitation, “a fifth conductive film spaced from the second conductive film in a planar direction intersecting the stacking direction, the fifth conductive film being at a position along the stacking direction that is closer to second chip than is than the first conductive film”. Claims 9-20 are dependent upon Claim 8.
Claims 2-5 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claim 2, the closest available prior art, that of Tagami, alone or in any reasonable combination with any other reference available, fails to teach the limitation, “a fifth conductive film spaced from the first stacked body in the planar direction to a side opposite the second conductive film, the fifth conductive film being at a position along the stacking direction that is closer to the second chip than is the first conductive film, a third plug between the first conductive film and the fifth conductive film in the stacking direction and connecting the first conductive film and the fifth conductive film”. Claim 3 is dependent upon Claim 2.
Regarding Claim 4, the closest available prior art, that of Tagami, alone or in any reasonable combination with any other reference available, fails to teach the limitation, “the second chip further includes: a sixth conductive film above the second stacked body in the stacking direction and extending across the second stacked body when viewed from the stacking direction, a seventh conductive film spaced from the second stacked body in the planar direction and at a position along the stacking direction that is closer to the first chip than is the sixth conductive film, a fourth plug between the sixth conductive film and the seventh conductive film in the stacking direction and connecting the sixth conductive film and the seventh conductive film”.
Regarding Claim 5, the closest available prior art, that of Tagami, alone or in any reasonable combination with any other reference available, fails to teach the limitation, “the third chip has an eighth conductive film connected to an end of the first semiconductor film, a width of the first conductive film in a lateral direction is greater than a width of the eighth conductive film in the lateral direction, the second chip has a ninth conductive film connected to an end of the second semiconductor film, and a width of the second conductive film in the lateral direction is greater than a width of the ninth conductive film in the lateral direction”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VICTOR J LASASSO whose telephone number is (703)756-5668. The examiner can normally be reached M-F 8-5 EST.
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/V.J.L./Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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