DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 7/6/26 has been entered.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 3-6, 10, 12-15, and 21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Election/Restrictions
Claims 7, 18-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention / species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 7/23/25.
Claim Objections
Claim 1 is objected to because of the following informalities: the word “and” was never deleted from line 6 of the original claim. However, the current and previous amendment does not show strikethrough or brackets for the missing word. Appropriate correction is required.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 3-6, 10, 12-15, and 21 have been considered but are moot because the new grounds of rejection addresses matters specifically challenged in the argument by using a new reference.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 3, 10, 12-15, 21-26 is/are rejected under 35 U.S.C. 103 as being obvious over U.S. Patent Application Publication No. 2021/0366547 (Oh) in view of U.S. Patent Application Publication No. 2023/0397446 (Nakaki).
The applied reference Nakaki has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2).
Oh discloses
1. (Currently Amended) A semiconductor memory device, comprising:
a first chip W2 that includes a first memory cell array MCA including a plurality of first memory cells MC and a first source layer ([0045]-[0047], [0068]-[0071]), a bit line BL electrically connected to the first memory cell array MCA, a first pad PAD2 electrically connected to the bit line BL; and
a second chip W3 that includes a second memory cell array MCA and a second pad PAD1, the second memory cell array MCA being electrically connected to a second source layer ([0045]-[0047], [0068]-[0071]) and the second pad PAD1, the second pad PAD1 being electrically connected to the first pad PAD2, the second memory cell array MCA and including a plurality of second memory cells MC,
wherein the second chip W3 is joined to the first chip W2 at a first joining surface ([0072]).
Oh fails to disclose
the second memory cell array shares the first bit line of the first chip with the first memory cell array.
Nakaki teaches
A semiconductor memory device comprising:
the second memory cell array 11_2 shares the first bit line BL of the first chip 10_1 with the first memory cell array 11_2.
It would have been obvious to a person of ordinary skill in the art at the time the invention was made to provide a shared bit line in Oh. The motivation would be to reduce chip area and bonding interconnects, to increase density, to shorten the electrical path, to reduce power consumption, and to reduce peripheral circuitry which is well known in the NAND flash art as taught by Nakaki ([0054]-[0058], [0160]). See MPEP 2144.03.
Oh discloses
3. (Currently Amended) The semiconductor memory device according to claim 1, wherein, when viewed in plan view from a direction in which the first chip and the second chip are stacked, the first pad Metal PAD2 and the second pad PAD1 are positioned at substantially the same positions.
Oh discloses
10. (Currently Amended) A semiconductor memory device, comprising:
a first memory chip W2 that includes a first memory cell array MCA including a plurality of first memory cells MC, a first source layer ([0045]-[0047], [0068]-[0071]) below the plurality of first memory cells MC in a first direction, and a plurality of bit lines BL above the plurality of first memory cells MC in the first direction and electrically connected to the first memory cells MC of the first memory cell array MCA, and a first pad PAD2 electrically connected to a bit line BL in the plurality of bits lines BL; and
a second memory chip W3 bonded to the first memory chip W2, the second memory chip W3 including a second pad PAD1 and a second memory cell array MCA including a plurality of second memory cells MC and a second source layer ([0045]-[0047], [0068]-[0071]) above the plurality of second memory cells MC in the first direction,
wherein the plurality of bit lines BL is between the first MCA and second memory arrays MCA and in the first direction, the second pad PAD1 being electrically connected to the first pad PAD2 and the second memory cell array MCA.
Oh fails to disclose
the plurality of bit lines is electrically connected to the second memory cells.
Nakaki teaches
A semiconductor memory device comprising:
the plurality of bit lines BL is electrically connected to the second memory cells 11_2.
It would have been obvious to a person of ordinary skill in the art at the time the invention was made to provide a plurality of bit line connected to the second memory cells in Oh. The motivation would be to reduce chip area and bonding interconnects, to increase density, to shorten the electrical path, to reduce power consumption, and to reduce peripheral circuitry which is well known in the NAND flash art as taught by Nakaki ([0054]-[0058], [0160]). See MPEP 2144.03.
Oh discloses
12. (Currently Amended) The semiconductor memory device according to claim 10, wherein, when viewed in plan view from the first direction, the first pad Metal PAD2 and the second pad PAD1are positioned at substantially the same positions.
Oh discloses
13. (Currently Amended) The semiconductor memory device according to claim 10, further comprising:
a controller chip ([0041], [0125]-[0130])) that includes a plurality of transistors, the controller chip being bonded to the first memory chip W2, wherein the first memory chip W2 is between the controller chip and the second memory chip W3 in the first direction.
Providing a controller chip in Oh with electrical connections would be based on suitability see MPEP 2144.07
14. (Original) The semiconductor memory device according to claim 13, wherein electrical connections between the controller chip ([0041], [0125]-[0130]) and the second memory chip W3 extend through the first memory chip W2.
Oh discloses
15. (Original) The semiconductor memory device according to claim 10, wherein the first memory chip W2 further includes a plurality of transistors X-HV ([0079]) below the first memory cell array MCA in the first direction.
Oh discloses
21. (Previously Presented) The semiconductor memory device according to claim 1, wherein the first memory cell array MCA is between the first source layer ([0045]-[0047], [0068]-[0071]) and the bit line BL, and the second memory cell array MCA is between the second source layer ([0045]-[0047], [0068]-[0071]) and the bit line BL.
Oh discloses
22. (New) The semiconductor memory device according to claim 1, wherein the first pad PAD2 is at the first joining surface.
Oh discloses
23. (New) The semiconductor memory device according to claim 22, wherein the second pad PAD1 is at the first joining surface and directly contacting the first pad PAD1.
Oh discloses
24. (New) The semiconductor memory device according to claim 10, wherein the first memory chip W2 is bonded to the second memory chip W3 at a first bonding interface, and the first pad PAD2 is at the first bonding interface.
Oh discloses
25. (New) The semiconductor memory device according to claim 24, wherein the second pad PAD1 is at the first bonding interface and adjacent to the first pad PAD2 in the first direction.
Oh discloses
26. (New) The semiconductor memory device according to claim 25, wherein the first pad PAD2 is bonded to the second pad PAD1.
Claim(s) 4-6 is/are rejected under 35 U.S.C. 103 as being obvious over Oh in view of Nakaki as applied to claim 3 above, and further in view of U.S. Patent Application Publication No. 2018/0261623 (Higashi), cited by Applicant.
The combination of references fails to teach
4. (Original) The semiconductor memory device according to claim 3, wherein the first pad and the second pad are bonded to one another at the first joining surface.
Higashi teaches (Fig. 1)
A semiconductor memory device comprising:
wherein the first pad 38b and the second pad 39a are bonded to one another at the first joining surface (between the two pads).
It would have been obvious to a person of ordinary skill in the art at the time the invention was made to bond the pads to each other in the modified device of Oh as a matter of routine engineering design considerations. See MPEP 2144.04. The motivation would be to prevent gaps between the bonding surfaces as taught by Higashi ([0062]).
Oh discloses (a third chip with a plurality of transistors, and third and fourth pads because this is mere duplication of parts (see MPEP 2144.04))
5. (Original) The semiconductor memory device according to claim 4, further comprising:
a third chip that includes a plurality of transistors and a third pad electrically connected to one of the plurality of transistors, wherein the third pad is bonded to a fourth pad at a second joining surface, and the fourth pad is electrically connected to the first memory cell array MCA of the first chip W2.
Oh disclose (a third chip with a plurality of transistors, and third - fifth pads because this is mere duplication of parts (see MPEP 2144.04))
6. (Currently Amended) The semiconductor memory device according to claim 4, further comprising:
a third chip that includes a plurality of transistors and a third pad electrically connected to one of the plurality of transistors, wherein the third pad is bonded to a fifth pad that is electrically connected to the bit line BL at a third joining surface.
This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. U.S. Patent No. 7,092,279 (Sheppard), U.S. Patent Application Publication Nos. 2021/0296298 (Sanuki), 2021/0125660 (Maejima), 2020/0365593 (Chen) teach stacked memory chips.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TERESA M ARROYO whose telephone number is (703)756-1576. The examiner can normally be reached Monday - Friday (8:30 A.M. E.T. - 5:00 P.M. E.T.).
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/TERESA M. ARROYO/ Primary Examiner, Art Unit 2893
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