DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I (claims 1-17) and Species A (Fig. 1, claims 1-6, 8, 10-15) in the reply filed on July 23, 2025 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 8, 10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Patent Application Publication No. 2010/0259975 (Toda).
Toda discloses (Figs. 3, 4, 7, 8, [0048], [0050], [0058])
1. (Original) A semiconductor memory device, comprising:
a first chip that includes a first memory cell array MA1 including a plurality of first memory cells and a first wiring layer 12bc (BL1) electrically connected to the first memory cell array MA1; and
a second chip that includes a second memory cell array MA2 electrically connected to the first wiring layer 12bc (BL1) and including a plurality of second memory cells,
wherein the second chip is joined to the first chip at a first joining surface 101c / 101d, and the second memory cell array MA2 shares the first wiring layer 12bc (BL1) of the first chip with the first memory cell array MA1.
Toda discloses (bit lines appear as a plurality in the Z direction in at least Fig. 5)
8. (Original) The semiconductor memory device according to claim 1, wherein the first wiring layer comprises a plurality of bit lines 12bc (BL1) shared by the first and second memory cell arrays MA1 and MA2.
Toda discloses (Figs. 3, 4, 7, 8, [0048], [0050], [0058])
10. (Original) A semiconductor memory device, comprising:
a first memory chip that includes a first memory cell array MA1 including a plurality of first memory cells and a plurality of bit lines 12bc (BL1) above the plurality of first memory cells in a first direction and electrically connected to the first memory cells of the first memory cell array MA1; and
a second memory chip bonded to the first memory chip, the second memory chip including a second memory cell array MA2 including a plurality of second memory cells,
wherein the plurality of bit lines 12bc (BL) is between the first and second memory arrays MA1 and MA2 in the first direction, and the plurality of bit lines 12bc (BL) is electrically connected to the second memory cells.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 2, 3, 11, 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Toda as applied to claim 1 or 10 above, and further in view of U.S. Patent Application Publication No. 2015/0162341 (Aritome).
Toda fails to specifically disclose
2. (Original) The semiconductor memory device according to claim 1, wherein the first chip further includes a first pad electrically connected to the first wiring layer, and the second chip further includes a second pad electrically connected to the first pad and the second memory cell array.
Toda fails to specifically disclose
11. (Original) The semiconductor memory device according to claim 10, wherein the first memory chip further includes a first pad electrically connected to a bit line in the plurality of bits lines, and the second chip further includes a second pad electrically connecting to the first pad to second memory cells.
Aritome teaches (Fig. 2)
A semiconductor memory device comprising:
wherein the first chip (MC array 110) further includes a first pad Metal 0.5 electrically connected to the first wiring layer BL / Metal 1, and the second chip (MC array 160) further includes a second pad Metal 2 electrically connected to the first pad Metal 0.5 and the second memory cell array MC 160.
It would have been obvious to a person of ordinary skill in the art at the time the invention was made to include pads in Toda. The motivation would be so that the pads may be electrically coupled to the wiring layers electrically coupled to the plurality of circuits formed in different regions as taught by Aritome ([0035]).
Aritome teaches
3. (Original) The semiconductor memory device according to claim 2, wherein, when viewed in plan view from a direction in which the first chip and the second chip are stacked, the first pad Metal 0.5 and the second pad Metal 2 are positioned at substantially the same positions.
Aritome teaches
12. (Original) The semiconductor memory device according to claim 11, wherein, when viewed in plan view from the first direction, the first pad Metal 0.5 and the second pad Metal 2 are positioned at substantially the same positions.
Claim(s) 4-6, 13-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Toda in view of Aritome as applied to claim 3 or 11 above, and further in view of U.S. Patent Application Publication No. 2018/0261623 (Higashi), cited by Applicant.
The combination of references fails to teach
4. (Original) The semiconductor memory device according to claim 3, wherein the first pad and the second pad are bonded to one another at the first joining surface.
Higashi teaches (Fig. 1)
A semiconductor memory device comprising:
wherein the first pad 38b and the second pad 39a are bonded to one another at the first joining surface (between the two pads).
It would have been obvious to a person of ordinary skill in the art at the time the invention was made to bond the pads to each other in the modified device of Toda as a matter of routine engineering design considerations. See MPEP 2144.04. The motivation would be to prevent gaps between the bonding surfaces as taught by Higashi ([0062]).
Toda discloses (a third chip with a plurality of transistors in Figs. 7, 8, 10 and third and fourth pads are mere duplication of parts (see MPEP 2144.04))
5. (Original) The semiconductor memory device according to claim 4, further comprising:
a third chip that includes a plurality of transistors and a third pad electrically connected to one of the plurality of transistors, wherein the third pad is bonded to a fourth pad at a second joining surface, and the fourth pad is electrically connected to the first memory cell array of the first chip.
Toda discloses (a third chip with a plurality of transistors in Figs. 7, 8, 10 and third - fifth pads are mere duplication of parts (see MPEP 2144.04))
6. (Original) The semiconductor memory device according to claim 4, further comprising:
a third chip that includes a plurality of transistors and a third pad electrically connected to one of the plurality of transistors, wherein the third pad is bonded to a fifth pad that is electrically connected to the second memory cell array of the second chip at a third joining surface.
Toda discloses (providing a controller chip as a third chip with a plurality of transistors in Figs. 7, 8, 10 would be based on suitability see MPEP 2144.07))
13. (Original) The semiconductor memory device according to claim 11, further comprising:
a controller chip that includes a plurality of transistors, the controller chip being bonded to the first memory chip, wherein the first memory chip is between the controller chip and the second memory chip in the first direction.
Toda discloses (Figs. 7, 8)
14. (Original) The semiconductor memory device according to claim 13, wherein electrical connections between the controller chip and the second memory chip extend through the first memory chip.
Toda discloses (a third chip with a plurality of transistors in Figs. 7, 8, 10)
15. (Original) The semiconductor memory device according to claim 10, wherein the first memory chip further includes a plurality of transistors below the first memory cell array in the first direction.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. Patent Application Publication Nos. 2009/0307415 (Kang), 2010/0032725 (Baba), 2011/0241225 (Inoue) teach stacked memory chips.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TERESA M ARROYO whose telephone number is (703)756-1576. The examiner can normally be reached Monday - Friday (8:30 A.M. E.T. - 5:00 P.M. E.T.).
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/TERESA M. ARROYO/ Primary Examiner, Art Unit 2893