Prosecution Insights
Last updated: October 01, 2026
Application No. 18/176,474

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR STORAGE DEVICE

Non-Final OA §103
Filed
Feb 28, 2023
Priority
Jun 21, 2022 — JP 2022-099892
Examiner
PURVIS, SUE A
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
KIOXIA Corporation
OA Round
1 (Non-Final)
64%
Grant Probability
Moderate
1-2
OA Rounds
0m
Est. Remaining
76%
With Interview

Examiner Intelligence

Grants 64% of resolved cases
64%
Career Allowance Rate
57 granted / 89 resolved
-4.0% vs TC avg
Moderate +12% lift
Without
With
+11.8%
Interview Lift
resolved cases with interview
Typical timeline
3y 4m
Avg Prosecution
20 currently pending
Career history
125
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
47.4%
+7.4% vs TC avg
§102
27.2%
-12.8% vs TC avg
§112
21.5%
-18.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 89 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Claims 7 and 9-20 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on July 30, 2025. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 5, 6, and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Fujii et al. (US 2014/0145338 A1) in view of Kim et al. (US 2023/0113465 A1). Fujii teaches claim 1 a semiconductor device (100), comprising: a first chip (10) that includes a first electrode (4) and a second electrode (5); and a second chip (20) that includes a third electrode (7) and a fourth electrode (8), the second chip being bonded to the first chip with the third electrode (7) in contact with the first electrode (4) and the fourth electrode (8) in contact with the second electrode (5) (See ¶¶0054-0058). Fujii fails to detail the electrode thickness and bonding interface as detailed in the claim. Kim discloses an asymmetric pad structure in which a first/rear bonding pad has a thickness T1 and a second / front bonding pad has a second thickness T2, where T1 is less than T2. Kim additionally discloses a bonding pad width W1 greater than the opposing pad’s width W2 (¶0044, ¶0049). It would have been obvious to a person of ordinary skill in the art before the filing date of the invention to modify Fujii’s corresponding bonded electrode pairs using Kim’s asymmetric pad geometry, because Fujii and Kim address the shared objectives of improve shared objectives of improving bonding alignment tolerance, reducing voids, and maintaining reliable electrode-to-electrode contact. Applying Kim’s geometry to Fujii’s bonded electrode arrangement would result in a first electrode having a thickness less than that of the second electrode while having a greater bonding-interface area than the second electrode. In particular, Kim teaches that a wider bonding pad provides an increased alignment margin, while a thickness difference between opposing bonding pads promotes stable bonding and reduces formation of voids during bonding. A person of ordinary skill in the art would therefore have reasonably expected that applying Kim’s asymmetric width and thickness relationship to Fujii’s bonded electrode pairs would improve tolerance to lateral misalignment and thermal expansion while maintaining a sufficient metal-to-metal bonding area and reliable electrical connection. The modification would use known bonding-pad dimensions for their known functions and would have produced predictable results. Regarding claim 5, Fujii in view of Kim teach the semiconductor device according to claim 1, wherein the second chip in Fujii discloses a fifth electrode that is in contact with the first electrode (See Fujii ¶¶0047-0053). Fujii discloses first and second semiconductor members having multiple electrode structures that are bonded at a bonding interface. Kim teaches providing an additional electrode on the second chip that contacts the first electrode, thereby allowing multiple bonding pads on one chip to be bonded to a common electrode on the other chip (see Kim ¶¶0107-0111). Regarding claim 6, Fujii in view of Kim teach the semiconductor device according to claim 1. Fujii discloses bonded semiconductor members having electrode pads connected to wiring layers through vias (See Fujii ¶¶0047–0051 and ¶¶0065–0069). Kim further teaches that a first electrode is in contact with a first conductive layer and a second electrode is in contact with a second conductive layer, with each electrode electrically connected to its corresponding conductive layer (See Kim ¶¶0030, 0035, 0039, 0044–0047). A person of ordinary skill in the art would have been motivated to incorporate Kim’s conductive-layer-to-electrode connections into Fujii’s bonded electrode structure to provide separate electrical paths for the respective electrodes and to facilitate routing to underlying semiconductor circuitry. The modification would have involved the use of conventional wiring and via connections for their known purpose and would have produced predictable results. Regarding claim 8, Fujii in view of Kim teach the semiconductor device according to claim 1, wherein the first electrode, the second electrode, the third electrode, and the fourth electrode each comprise copper (See Fujii ¶¶0048, 0051). Claims 2 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Fujii in view of Kim as applied to claim 1 above, and further in view of Watanabe (US 2021/0280545 A1). Fujii in view of Kim teach the semiconductor device according to claim 1, but fails to teach the product of the first thickness and the first area is 80% to 120% of the product of the second thickness and the second area. Watanabe supplies thickness-controlled bonded pad structures, including exemplary thicknesses of approximately 300 nm and 500 nm (See Watanabe ¶¶0055, 0063). It would have been obvious to a person of ordinary skill in the art before the filing date of the invention to select the thicknesses and bonding-interface areas of Fujii’s bonded electrodes, as modified according to Kim, in view of Watanabe’s teaching of controlling the relative thicknesses of bonded pad structures. Kim teaches using differing pad widths and thicknesses to improve alignment tolerance, bonding stability, and resistance to void formation. Watanabe further teaches controlling pad thickness to reduce bonding-related electrical problems. Because the amount of metal available for thermal expansion is related to the product of pad thickness and bonding-interface area, a person of ordinary skill in the art would have adjusted the pad dimensions to provide approximately balanced effective pad volumes. Such adjustment would have involved routine optimization of known result-effective variables and would have produced predictable bonding improvements. The resulting dimensions would have provided a product of the first thickness and first area within approximately 80% to 120% of the product of the second thickness and second area. Regarding claim 4, Fujii in view of Kim teach the semiconductor device according to claim 1, but fails to teach wherein the second thickness is 1.5 times to 10 times greater than the first thickness. Kim discloses asymmetric bonding pads in which one pad is thinner than the opposing pad; and one pad is wider than the opposing pad. Kim’s thickness relationship corresponds generally to T1 < T2 (see Kim ¶0044 and claim 7). Watanabe discloses bonded connection pads and dummy pads having different thicknesses. In an exemplary embodiment, dummy-pad thickness: approximately 300 nm and connection-pad thickness approximately 500 nm which falls within the claimed range of 1.5 to 10 (See Watanabe ¶¶0055, 0063). It would have been obvious to modify Fujii’s bonded electrode pairs using Kim’s asymmetric bonding-pad arrangement and Watanabe’s thickness-controlled pad structures. Kim teaches that differing bonding-pad thicknesses, together with differing pad widths, improve alignment tolerance, stabilize bonding, and reduce void formation. Watanabe further teaches forming bonded pad structures with different thicknesses, including a thinner pad of approximately 300 nm and a thicker pad of approximately 500 nm. A person of ordinary skill in the art would have been motivated to select the relative thicknesses of Fujii’s bonded electrodes within the disclosed and predictable range to improve bonding reliability and reduce bonding defects. The exemplary thickness ratio of approximately 500/300=1.67 satisfies the limitation that the second thickness is 1.5 to 10 times the first thickness. Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Fujii in view of Kim as applied to claim 1 above, and further in view of Kagawa et al. (US 2016/0343763 A1). Fujii in view of Kim teach the semiconductor device according to claim 1, but fails to disclose wherein the product of the first thickness and the first area is greater than the product of the second thickness and the second area (Fujii ¶¶0046-0058; Kim provides asymmetric geometry ¶0044, ¶0049 and claim 7). Kagawa expressly teaches unequal joining-side areas with a first Cu joining portion 416 has a larger joining-side area; and second Cu joining portion 426 has a smaller joining-side area (See Kagawa ¶¶0254–0255). Kagawa explains that the area difference is selected to accommodate estimated bonding misalignment and avoid contact between an electrode and an opposing insulating film (See ¶¶0255, 0289–0292). It would have been obvious to one having ordinary skill in the art before the invention to configure Fujii’s bonded electrode pairs according to Kim’s asymmetric thickness and width arrangement and Kagawa’s unequal joining-area arrangement. Kim teaches that a thinner but wider bonding pad improves alignment margin, while the opposing thicker pad promotes stable bonding and reduces void formation. Kagawa further teaches that one joining electrode may have a greater bonding-interface area than the opposing joining electrode to accommodate bonding misalignment and prevent contact with an opposing insulating film. A person of ordinary skill in the art would have selected the relative thicknesses and bonding-interface areas to provide a desired thermal-expansion and bonding-reliability relationship with a predictable optimization of the known pad-width and pad-thickness parameters. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUE A PURVIS whose telephone number is (571)272-1236. The examiner can normally be reached M-F 0830 to 1630. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Feb 28, 2023
Application Filed
Sep 23, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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SEMICONDUCTOR DEVICE AND WAFER
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SENSING DEVICE AND FABRICATING METHOD OF THE SAME
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Patent 12740482
SEMICONDUCTOR PACKAGE
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Patent 12707947
STRUCTURES FOR REDUCING GAP FILL DEFECTS IN A VERTICALLY STACKED SEMICONDUCTOR DEVICE AND METHODS FOR FORMING THE SAME
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Patent 12702020
METAL COMPONENT
4y 5m to grant Granted Aug 04, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
64%
Grant Probability
76%
With Interview (+11.8%)
3y 4m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 89 resolved cases by this examiner. Grant probability derived from career allowance rate.

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