DETAILED ACTION
Claims 1-2 and 4-5 have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
For future reference, when making amendments, arguments, etc., please refer to the paragraph numbers in the filed specification, not in the published specification (e.g. instead of amending paragraph 40, applicant should have amended paragraph 38). When paragraph numbers differ between the specifications, as they do in this case, confusion may result.
Claim Recommendations
The examiner recommends the following for improved/easier readability:
In claim 1, lines 4-5, rewording to --generating, by a central processor, a plurality of original setting commands, wherein…--.
In claim 1, line 9-10, rewording to --merging, by the central processor, the first original register setting commands to generate at least one merged register setting command; and--.
In claim 1, lines 11-12, rewording to --transmitting, by the central processor, the at least one merged register setting command to the co-processor,--.
In claim 1, line 18, inserting --the-- before “sorting”. A similar recommendation is made for claim 4.
In claim 1, lines 21-23, rewording to --performing pseudo execution on the original register setting commands, by the central processor, to…commands; and--.
In claim 1 (and similarly claim 4), combining the “combining…” paragraph and the “converting…” paragraph. Please ensure all limitations from both paragraphs are retained.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-2 and 4-5 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Referring to claim 1 (and similarly claim 4), the examiner has been unable to find support in the parent application for the combination of the pseudo-execution using a buffer region and the claimed sorting. The pseudo-execution/buffer embodiment is described in at least paragraphs 40-41, which discuss pseudo-executing the unsorted commands of Table 7 in order. The sorted commands of Table 8 are not what are pseudo-executed using the buffer region(s). Absent applicant identifying support for this combination, it appears applicant will have to delete the sorting step and any subsequent reference thereto.
Further referring to claim 1 (and similarly claim 4), in the last paragraph, the examiner has been unable to find support in the parent application for the first alternative (converting a same buffer region) being used in combination with another portion of the claim. Specifically, the first alternative is claimed as part of the operation of merging the first original register setting commands (line 13), which have “continuous addresses of a plurality of registers” (lines 16-17). The first alternative, however, appears to be worded to cover a single/same buffer region, i.e., register (from paragraphs 39-40 and 43). A single register cannot have continuous addresses of a plurality of registers. This alternative is described as converting a single register/buffer region that needs to be written to multiple times (e.g. by commands 1, 3, 9, 11, 13, etc., i.e., those that write to group 1, offset 2), and not to multiple registers having address continuity. Thus, please delete the first alternative from the end of claim 1 or explain how this is compatible with previous parts of the claim.
Claims 2 and 5 are rejected due to their dependence on a claim lacking adequate written description.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-2 and 4-5 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The claims recite the following limitations for which there is a lack of antecedent basis:
In claim 1, line 17, “the setting targets of the first original register setting commands having continuous addresses of a plurality of registers”. In line 7, applicant refers to having address continuity, which is not necessarily the same as having continuous addresses of a plurality of registers. Applicant should use consistent language. Another reference to the former is in the 2nd to last line. Therefore, please replace “have address continuity” with --having continuous addresses of a plurality of registers--.
In claim 4, “the setting targets having continuous addresses of a plurality of registers”, for similar reasoning.
All dependent claims are rejected due to their dependence on an indefinite claim.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-2 and 4-5 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Regarding step 1 of the Subject Matter Eligibility Test (hereafter “SMET”) (MPEP 2106(III)), claims 1-2 are directed to a process, and claims 4-5 are directed to a machine.
Referring to step 2A (prong 1) of the SMET (MPEP 2106.04(II)(A)), claim 1 recites:
merging first original register setting commands to generate at least one merged register setting command, wherein the first original register setting commands are of original register setting commands, a plurality of setting targets of the first original register setting commands have address continuity, and each of the original register setting commands is adapted to set at least one bit of at least one register of a co-processor;
wherein the operation of merging the first original register setting commands comprises:
sorting the original register setting commands according to addresses of a plurality of setting targets of the original register setting commands;
combining the first original register setting commands with the setting targets of the first register setting commands having continuous addresses of a plurality of registers into the at least one merged register setting command after sorting is completed;
performing pseudo execution on the original register setting commands; and
scanning, after the pseudo execution of the original register setting commands is completed, so as to convert a same entry filled with at least one setting value into the at least one merged register setting command or convert a plurality of entries filled with a plurality of setting values and having continuous addresses into the at least one merged register setting command.
All of these steps amount to a mental process that can be practically performed in the human mind, including with the aid of pen and paper. See MPEP 2106.04(a). For instance, presented with the example commands that, as a result of their encoded format, would set a coprocessor register bit, have address continuity, etc., a human would be able to convert the commands mentally, with the aid of pen and paper, into merged commands using the tables and algorithms shown in paragraphs 33-43 of the specification. A human could simply create the tables having entries on paper and write data therein to carry out the claimed merging algorithm, as applicant has demonstrated in the specification. The examiner notes that pseudo execution is simply a phrase that describes filling out table entries (paragraphs 40+).
Referring to step 2A (prong 2) of the SMET (MPEP 2106.04(II)(A)), claim 1 recites the following additional elements:
the claimed merging is performed by a central processor;
transmitting the at least one merged register setting command to the co-processor by the central processor;
initializing at least one buffer region, wherein the at least one buffer region corresponds to the at least one register of the co-processor in a one-to-one manner;
performing the pseudo execution to fill in the at least one buffer region with a plurality of setting values of the original register setting commands by the central processor;
scanning the at least one buffer region; and
generating a plurality of original register setting commands by a central processor.
Use of a highly generic central processor and at least one buffer region (generic memory,
which records data just as table entries on paper record data) amounts to use of a generic computer as a tool to perform the abstract idea (mental process), which, per the courts, does not integrate the abstract idea into a practical application (MPEP 2106.04(d)(I), 6th bullet).
The transmitting, initializing (storing), and filling in of (storing to) the buffer region
correspond to insignificant extra-solution activity that is incidental to the mental process and which is a nominal/tangential addition to the claim. Per the courts, such activity does not integrate the abstract idea into a practical application (MPEP 2106.04(d)(I), 7th bullet).
A central processor generating commands for a co-processor is a generic computer being used as a tool to implement the abstract idea (commands must be generated before they can be merged), which, as explained above, does not integrate the abstract idea into a practical application. Further, generating commands is deemed insignificant pre-solution activity, which, as explained above, does not integrate the abstract idea into a practical application.
Referring to step 2B of the SMET (MPEP 2106(III)):
The generic central processor and buffer region do not amount to significantly more, per the courts (MPEP 2106.05(I), 2nd element (i), and MPEP 2106.05(f)).
The transmission has been deemed by the courts to be a well-understood, routine, and conventional activity that does not amount to significantly more (MPEP 2106.05(d)(II), element (i)).
The initializing, which could be interpreted to be a storing of data for the very first command into a table (e.g. see p.20, lines 1-3, where the initializing would involve writing 0x000000FF and 0x00000078 to entry 1,2 in Table 12). This storing has been deemed by the courts to be a well-understood, routine, and conventional activity that does not amount to significantly more (MPEP 2106.05(d)(II), element (iv)).
Filling in a memory storing the table is again just writing data to memory, which has been deemed by the courts to be a well-understood, routine, and conventional activity that does not amount to significantly more (MPEP 2106.05(d)(II), element (iv)).
Finally, the generating of commands is well-understood, routine, or conventional, as evidenced by Wyatt, US 2012/0236013, which states “In a conventional system, the CPU 102 sends commands and data to the GPU 240 via the graphics driver 103. These commands and data may be transmitted over communications path 113” (paragraph 76). Thus, a conventional CPU generates commands to be sent to a co-processor and this is not significantly more.
Thus, claim 1 is subject matter-ineligible (hereafter “SMI”).
Referring to claim 2, applicant merely adds more generic computing elements that are part of a computer to perform the abstract idea, which, as stated above, does not integrate or amount to significantly more. Alternatively, applicant also appears to be attempting to generally link the mental process to a processor/GPU environment, where a GPU includes registers to store drawing/graphics data. Per the courts, this linking does not integrate the abstract idea into a practical application (MPEP 2106.04(d)(I), 8th bullet), or amount to significantly more (MPEP 2106.05(I)(A), last element (iv))). Also, see MPEP 2106.05(h). Thus, claim 2 is SMI.
Claims 4-5 are SMI for similar reasoning as claims 1-2, respectively. Note that where the central processor is claimed to perform various steps, this does not integrate or amount to significantly more for similar reasoning given above.
Allowable Subject Matter
Claims 1-2 and 4-5 are allowed over the prior art.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 1 and 4, the prior art of record has not taught, either individually or in combination, and together with all other claimed features, the limitations of the last three paragraphs.
Response to Arguments
On pages 9-10 of applicant’s response, applicant argues that the invention transmits fewer commands, thereby improving speed and performance of both the central processor and co-processor. Additionally, applicant argues that the invention reduces bandwidth needed to transmit the commands.
The examiner acknowledges that transmitting merged commands would result in reduced traffic/bandwidth and number of commands that need to be processed by the coprocessor. Ultimately, however, the transmitting is not the source of improvement. The transmission logic will simply transmit whatever is sent to it, i.e., unmerged commands or merged commands. The improvement stems from the mental process itself, which merges commands to result in less data to transmit. Per MPEP 2106.05(a), “the judicial exception alone cannot provide the improvement… the improvement can be provided by the additional element(s) in combination with the recited judicial exception.”
Regarding applicant’s comparison to example 47, this is not persuasive because the examiner sees a difference in examining network packets in real time (which a human cannot reasonably do given the speeds at which packets are transmitted), and merging example commands presented to a human using the described algorithms in applicant’s specification. There is nothing about real-time processing or high-volume data in the claims that would make the mental process impractical.
Applicant’s argument related to examples 40 and 23 are not persuasive because applicant does not have claimed at least one additional element that realize(s) an improvement. Again, the examiner maintains that the improvement comes from the merging. All limitations apart from the mental process are either highly generic computing components or insignificant extra-solution activity.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to David J. Huisman whose telephone number is 571-272-4168. The examiner can normally be reached on Monday-Friday, 9:00 am-5:30 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta, can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/David J. Huisman/Primary Examiner, Art Unit 2183