DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/5/2025 has been entered.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-3, 4, 6, 9 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over Han (US 11,543,919) in view of Loose (US 2004/0227832) and further Tada ( US 2004/0043676) and Wang (US 2020/0211457) .
Regarding claims 1-3, Han teaches A display device, comprising: a base layer (Fig. 1 layer 10); a circuit layer disposed on the base layer(Fig. 1 layer 12); and an element layer disposed on the circuit layer and comprising a light emitting element and a light receiving element (Fig. 1 layer 14), wherein the circuit layer comprises: a pixel driving circuit connected to the light emitting element; a sensor driving circuit connected to the light receiving element; a plurality of reset voltage wirings disposed in an active area ([0079] sensor driving circuit. It is understood that the sensor driving circuit would include the reset voltage wirings TG.) and configured to provide a reset voltage to the sensor driving circuit ([0213-0215] teaches sensor driving circuit is reset during rest time (to). Although Han teaches the limitations as discussed above, he fails to teach a reset voltage reinforcement wiring disposed in a peripheral area, which is adjacent to the active area, and connected to the plurality of reset voltage wirings and extending in a first direction.
However in the field of driving a panel with a sensor device, Loose teaches a system with individual pixel reset where a first reset voltage reinforcement wiring disposed in a peripheral area, which is adjacent to the active area, and connected to the plurality of reset voltage wirings and extending in a first direction (Figs. 3 and 5 Reset voltage sources 19), .
Therefore it would have been obvious to one of ordinary skill in the art to combine the device as taught by Han with voltage source method as taught by Loose. This combination would allow and individual pixel reset for a imaging sensor as taught by Loose. Although the combination teaches combination as discussed above but fail to teach a first driving voltage wiring disposed in the peripheral area and configured io provide a driving voltage to the pixel driving circuit, wherein the first driving voltage wiring is disposed closer to the active area than the first reset voltage reinforcement wiring.
However in the field of driving a sensor display device, Tada teaches a first driving voltage wiring disposed in the peripheral area and configured io provide a driving voltage to the pixel driving circuit, wherein the first driving voltage wiring is disposed closer to the active area than the first reset voltage reinforcement wiring (Fig. 1 shows sensor control circuit 5 farther away from active area than scan line driving circuit 3 and Fig. 3 shows a reset signal line RST connected to transistor Q4 for image acquisition 12a and 12b. [0053] teaches sensor control circuit 5 controls sensors for image acquisition. [0054] teaches image acquisition sensor 12a and 12b for each pixel. [0056] teaches reset transistor Q4 initializes the buffer 13 and the capacitor C3. Based on these teachings it is clear the sensor control circuit functions as a reset reinforcment wiring to supply a reset signal the reset signal line RST) .
Therefore it would have been obvious to one of ordinary skill in the art to combine the device as taught by Han with voltage source method as taught by Loose and the manufacturing method as taught by Tada. This combination would allow and individual pixel reset for a imaging sensor as taught by Loose. Although the combination teaches the limitations as discussed above, they do not explicitly teach wherein the reset voltage and the first driving voltages are DC voltages.
However in the field of supplying voltages for a display device, Wang teaches a display device where reset voltage and first driving voltages are DC voltages ([0050]).
Therefore it would have been obvious to one of ordinary skill in the art to combine the device as taught by Han with voltage source method as taught by Loose and the manufacturing method as taught by Tada and voltage supply method as taught by Kim. This combination would allow and individual pixel reset for a imaging sensor as taught by Loose
Regarding claim 2, Loose discloses the claimed invention reset voltage reinforcement wiring(Figs. 3 and 5 Reset voltage sources 19) except for wherein the reset voltage reinforcement wiring has a bar shape extending in one direction. It would have been an obvious matter of design choice to make the reinforcement wiring shape since the applicant has not disclosed that bar extending in one direction solves any stated problem or is for any particular purpose and it appears that the invention would perform equally well with the reinforcement wiring as disclosed by Loose.
Regarding claim 3, Loose teaches wherein the peripheral area comprises a first peripheral area defined on an upper side of the active area and a second peripheral area disposed on a lower side of the active area (Fig. 5 shows an upper side, lower side, right side and left side of a peripheral area), a first reset voltage reinforcement wiring disposed in the first peripheral area (Fig. 5 reset voltage sources 19).
Allowable Subject Matter
Claims 18 and 22-24 are allowed.
Claims 4, 6 and 9 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 4 is indicated as allowable based one the layer composition in combination with the limitations of the intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDRE L MATTHEWS whose telephone number is (571)270-5806. The examiner can normally be reached Mon-Fri 9:00-6:00.
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/ANDRE L MATTHEWS/ Primary Examiner, Art Unit 2621