A u-shape DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 7/9/2026 has been entered.
Status of the Application
Acknowledgement is made of the amendment received on 7/9/2026. Claims 1-5 and 7-23 are pending in this application. Claim 1 is amended. Claim 6 is canceled. Claims 11-23 remain withdrawn.
Claims 1-5 and 7-10 are presented in this Office Action.
Priority
Acknowledgment is made of applicant’s claim for foreign priority based on an application JP 2020-156726 filed in Japan Patent Office (JPO) on 9/17/2020 and receipt of a certified copy thereof.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Saito et al. (US 2016/0240561; hereinafter ‘Saito’) in view of Xu et al. (US 2019/0067525; hereinafter ‘Xu’), and Watanabe et al. (US 2015/0255518; hereinafter ‘Watanabe’).
Regarding claim 1, Saito teaches an image display device manufacturing method (the manufacturing of LED display device, [0003]) comprising:
preparing (shown in FIG. 1, [0023]) a semiconductor layer (the stacked semiconductor structure including 11, 12, 13, [0024]; hereinafter ‘SL’) comprising a light-emitting layer (13);
bonding (shown in FIG. 12, [0109]) the semiconductor layer (SL) to a first surface (the surface facing 11, [0112]) of a light-transmitting substrate (the light-transmitting substrate including 121, 122; 131, 132; 141, 142, [0112]; hereinafter the light-transmitting substrate is referred to as ‘LTS’, and its first surface is referred to as ‘LTSF’);
UP’);
forming (shown in FIG. 13) a first insulating film (31 and 32 of 30, [0037, 0047]; hereinafter ‘IF1’), covering the first surface of the light-transmitting substrate (LTSF) and the light-emitting element (10);
forming a light-blocking layer (the interconnects 23 and 24 including a light-reflective metal material, FIG. 5, [0078]; hereinafter ‘LBL’);
after forming the light-blocking layer (LBL), forming a circuit element (TFT 20, FIG. 5, [0026]) above the light-blocking layer (20 is provided above LBL, FIG. 5);
forming a second insulating film (34 of 30, FIG. 1, [0037]) covering the first insulating film (IF1) and the circuit element (20);
forming a first via (the first via extending vertically from e2, FIG. 1, [0028]; hereinafter ‘V1’) the via (V1) passing through the first insulating film (IF1) and the second insulating film (34); and
forming a first wiring layer (the first wiring layer is the conductive layer formed on 34, FIG. 1; hereinafter ‘W1’) on the second insulating film (34), wherein:
the first via (V1) is located between the first wiring layer (W1) and the upper surface of the light-emitting element (10UP), and electrically connects (shown in FIG. 1) the first wiring layer (W1) and the upper surface of the light-emitting element (10UP).
Saito does not teach the image display device manufacturing method comprising: etching the semiconductor layer on the first surface of the light-transmitting substrate.
Xu teaches an image display device manufacturing method [0006] comprising: etching (etching, FIG. 2, [0022]) the semiconductor layer (120) on the first surface of the light-transmitting substrate (the surface of 102 facing 120).
As taught by Xu, one of ordinary skill in the art would utilize and modify the above teaching into Saito to obtain and achieve the image display device manufacturing method comprising etching the semiconductor layer on the first surface of the light-transmitting substrate as claimed, because it facilitates stable handling of the epitaxial layer and enables subsequent patterning of trenches and through-hole with respect to the final device configuration [0022, 0036].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Xu in combination with Saito due to the above reason.
Saito in view of Xu does not teach the image display device manufacturing method comprising: in a plan view, the circuit element does not overlap the light-emitting element.
Watanabe teaches an image display device (FIG. 12B, [0048]) comprising: in a plan view, a circuit element (transistor 103, [0458]) does not overlap a light-emitting element (103 laterally spaced apart from a light-emitting element 107, such that 103 and l07 do not overlap in the illustrated projection, [0458]).
As taught by Watanabe, one of ordinary skill in the art would utilize and modify the above teaching into Saito in view of Xu to obtain and achieve the image display device manufacturing method comprising in a plan view, the circuit element does not overlap the light-emitting element as claimed, because locating the circuit element in a light-blocked non-emission region prevents the transistor electrodes and wirings from being visually recognized and suppresses undesired light leakage, thereby improving display quality [0519, 0565-0567].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Watanabe in combination with Saito in view of Xu due to the above reason.
Regarding claim 2, Saito in view of Xu and Watanabe teaches the image display device manufacturing method according to claim 1, further comprising: before the step of bonding the semiconductor layer, roughening (Saito: shown in FIG. 3, [0070]) an exposed surface (11a) of the semiconductor layer (SL) to form a roughened surface (11p forms on 11a).
Saito in view of does not teach the image display device manufacturing method further comprising forming a film having light transmittance across the exposed surface.
Xu teaches the image display device manufacturing method further comprising forming a film (130, FIG. 2, [0022]) having light transmittance (130 is a transparent bonding layer) across the exposed surface (the surface of 120 facing 102).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Xu to obtain and achieve the image display device manufacturing method further comprising forming a film having light transmittance across the exposed surface as claimed, because providing a bonding film serves to planarize the bonding surface and enhance bonding reliability [0015].
Regarding claim 3, Saito in view of Xu and Watanabe teaches the image display device manufacturing method according to claim 1, further comprising:
forming (Saito: shown in FIG. 13) a second via (the second via extending vertically from e1, [0028]; hereinafter ‘V2’) passing through the first insulating film (IF1) and the second insulating film (36), wherein
the light-emitting element (10) comprises a connecting portion (e1), and
the second via (V2) is located between and electrically connects (shown in FIG. 13) the first wiring layer (W1) and the connecting portion (e1).
Regarding claim 7, Saito in view of Xu and Watanabe teaches the image display device manufacturing method according to claim 1, further comprising: before the step of forming the first insulating film (Saito: IF1, FIG. 13), forming a third wiring layer (e2, [0028]) covering the light-emitting element (e2 covering 10).
Regarding claim 8, Saito in view of Xu and Watanabe teaches the image display device manufacturing method according to claim 1, wherein: the semiconductor layer comprises a gallium nitride compound semiconductor (Saito: SL includes a gallium nitride compound semiconductors, and [0043, 0117]).
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Saito (US 2016/0240561) in view of Xu (US 2019/0067525), and Watanabe (US 2015/0255518), and future in view of Hwang et al. (Microelectronic Engineering 77, 71-75, 2005; hereinafter ‘Hwang’).
Regarding claim 4, Saito in view of Xu and Watanabe teaches the image display device manufacturing method according to claim 1, Saito in view of Watanabe does not teach the image display device manufacturing method further comprising: before the step of bonding the semiconductor layer, forming a conductive layer having light transmittance on the semiconductor layer; and after the step of bonding the semiconductor layer, etching the conductive layer to form a second wiring layer.
Xu teaches the image display device manufacturing method further comprising
before the step of bonding the semiconductor layer, forming a conductive layer (114 is an N-type ohmic contact layer, FIG. 1, [0021]) on the semiconductor layer (120); and
after the step of bonding the semiconductor layer, etching (114 is patterned by lithography, , FIG. 2, [0033]) the conductive layer (114) to form a second wiring layer (114 forms an ohmic contact region of 182, [0022]).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Xu to obtain and achieve the image display device manufacturing method further comprising: before the step of bonding the semiconductor layer, forming a conductive layer on the semiconductor layer; and after the step of bonding the semiconductor layer, etching the conductive layer to form a second wiring layer as claimed, because it serves as a conductive layer forming part of a conductive path connecting the semiconductor layer and the electrode, thereby facilitating current flow through the device [0021, 0035, 0039].
Saito in view of Xu and Watanabe does not teach that the N-type ohmic contact layer having light transmittance.
Hwang teaches an image display device manufacturing method (1. Introduction) comprising N-type ohmic contact layer (ITO) having light transmittance (ITO is the transparent layer, abstract).
As taught by Hwang, one of ordinary skill in the art would utilize and modify the above teaching into Saito in view of Xu and Watanabe to obtain and achieve the image display device manufacturing method further comprising forming a conductive layer having light transmittance as claimed, because ITO is a known material and widely used for transparent electrode in the art (1. Introduction). Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Hwang in combination with Saito in view of Xu and Watanabe due to the above reason.
Regarding claim 5, Saito in view of Xu, Watanabe, and Hwang teaches the image display device manufacturing method according to claim 4, further comprising:
forming (Saito: shown in FIG. 13) a second via (the second via extending vertically from e1, [0028]; hereinafter ‘V2’) passing through the first insulating film (IF1) and the second insulating film (36), wherein
the second via (V2) is located between and electrically connects (shown in FIG. 13) the first wiring layer (W1) and the connection portion (e1).
Although, Saito describes the second via as electrically connecting the first wiring layer and a connection portion, the connecting portion of Saito corresponds to an electrode.
Xu teaches that the second wiring layer functions as an ohmic contact region of an electrode 182 (FIG. 2, [0021-0022]).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Saito in view of Xu to obtain and achieve the image display device manufacturing method further comprising the second via is located between and electrically connects the first wiring layer and the second wiring layer as claimed, because the connection portion of Saito and the second wiring layer of Xu are functionally equivalent as electrodes.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Saito (US 2016/0240561) in view of Xu (US 2019/0067525), and Watanabe (US 2015/0255518), and future in view of Shin et al. (US 2018/0308420; hereinafter ‘Shin’).
Regarding claim 9, Saito in view of Xu and Watanabe teaches the image display device manufacturing method according to claim 1, further comprising: forming a wavelength conversion member (Saito: 121, 122, FIG. 12, [0111]).
Saito in view of Xu and Watanabe does not teach the image display device manufacturing method comprising forming a wavelength conversion member on a second surface of the light-transmitting substrate located on a side opposite to the first surface of the light-transmitting substrate.
Shin teaches the image display device manufacturing method [0010] further comprising: forming (shown in FIG. 1) a wavelength conversion member (150, 160, and 170, [0049]; hereinafter ‘WCM’) on a second surface of the light-transmitting substrate (the surface of 110 on which WCM is formed, [0037, 0046]) located on a side opposite to the first surface of the light-transmitting substrate (the surface of 110 facing 120).
As taught by Shin, one of ordinary skill in the art would utilize and modify the above teaching into Saito in view of Xu and Watanabe to obtain and achieve the image display device manufacturing method comprising forming a wavelength conversion member on a second surface of the light-transmitting substrate located on a side opposite to the first surface of the light-transmitting substrate as claimed, because it provides a flat and stable surface that facilitates easy application and patterning of the color conversion materials, thereby improving manufacturability [0058].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Shin in combination with Saito in view of Xu and Watanabe due to the above reason.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Saito (US 2016/0240561) in view of Xu (US 2019/0067525), and Watanabe (US 2015/0255518), and future in view of Choi et al. (US 2020/0168663; hereinafter ‘Choi’).
Regarding claim 10, Saito in view of Xu and Watanabe teaches the image display device manufacturing method according to claim 1, but does not teach the image display device manufacturing method further comprising: removing the light-transmitting substrate and forming a wavelength conversion member in place of the light-transmitting substrate.
Choi teaches the image display device manufacturing method [0002] further comprising: removing (shown in FIG. 16) the light-transmitting substrate (460 is etched to form a window region, [0144]) and forming (shown in FIG. 18) a wavelength conversion member (481, 482, 483, [0146]) in place of the light-transmitting substrate (shown in FIG. 18).
As taught by Choi, one of ordinary skill in the art would utilize and modify the above teaching into Saito in view of Xu and Watanabe to obtain and achieve the image display device manufacturing method further comprising: removing the light-transmitting substrate and forming a wavelength conversion member in place of the light-transmitting substrate as claimed, because removing the light-transmitting substrate creates a direct light-emission window that reduces optical loss and increases light transmission efficiency [0144]. Further the wavelength conversion member is formed on the light-emission side opposite the driving layer to convert light emitted from the active layer into different colors while avoiding interference with the driving circuitry and securing a light-emitting region [0077, 0145].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Choi in combination with Saito in view of Xu and Watanabe due to above reason.
Response to Arguments
Applicant's arguments with respect to claims have been considered but are moot in view of the new ground of rejection. Response to arguments on newly added limitations are responded to in the above rejection.
Applicant submits, in page 10 of Remark, that
“The combination of Saito, Xu, and Liu does not teach or suggest the combination of features recited in amended claim 1.
For example, the combination of Saito, Xu, and Li does not teach or suggest a method that include “after forming the light-blocking layer, forming a circuit element above the light-blocking layer””.
The examiner respectfully disagrees.
Amended claim 1 incorporates the light-blocking layer limitation previously recited in claim 6. Consistent with the previous rejection of claim 6, Saito’s light-reflective interconnects 23 and 24 correspond to the claimed light-blocking layer. However, the present rejection does not rely on first gate electrode G1 as the claimed circuit element. Rather, TFT 20 corresponds to the circuit element and is formed above interconnects 23 and 24, as shown in FIG. 5.
Applicant submits, in page 10 of Remark, that
“Additionally, the combination of Saito, Xu, and Liu does not teach or suggest a method that includes "after forming the light-blocking layer, forming a circuit element above the light- blocking layer such that, in a plan view, the circuit element does not overlap the light-emitting element."”.
The examiner respectfully disagrees.
The present rejection further relies on Watanabe, rather than Liu, for the claimed non-overlapping arrangement. Watanabe teaches laterally spacing transistor 104 from light-emitting element 107 so that their projected regions do not overlap, while positioning the transistor in a light-blocked non-emission region to reduce visibility of the transistor electrodes and wirings and suppress undesired light leakage [0519, 0565-0567].
Applicant submits, in page 11 of Remark, that
“Saito and Liu are based on fundamentally different approaches to space utilization within a pixel region, and it would not have been obvious to modify Saito based on Liu.
In Saito, the light emitting region 10 and the first gate electrode G1 are arranged in a vertically stacked configuration. In other words, rather than arranging the light emitting region 10 and the first gate electrode G1 side-by-side in a planar direction, Saito adopts an arrangement in which the elements are disposed above and below one another. Such a configuration appears to be directed to efficient utilization of limited pixel area through vertical integration.
In contrast, Liu adopts a different arrangement approach, placing light-emitting elements near the corners of a pixel region and utilizing the resulting central space to accommodate a circuit component. In other words, rather than arranging the light-emitting element and the circuit component in a vertically stacked configuration, Liu adopts a planar arrangement in which the elements are laterally separated from one another”.
The examiner respectfully disagrees.
Applicant’s argument that a laterally separated arrangement is incompatible with Satio’s vertically stacked structure is not persuasive. The requirement that the circuit element be “above” the light-blocking layer does not require the circuit element to overlap the light-emitting element. The circuit element may remain vertically above the light-blocking layer while being laterally offset from the light-emitting element. Accordingly, the proposed modification preserves Satio’s vertical layer arrangement while providing Watanabe’s plan -view non-overlap and its associated display quality benefits.
Details included in the above rejection.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure in that Tanada (US 2011/0043098), Oda et al. (US 2012/0146028), and Yamazaki et al. (US 2020/0251547) teach display or semiconductor device including light-blocking layers, insulating films, and TFT circuit elements arranged relative to light-emitting or light-sensitive elements.
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/JIYOUNG OH/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 8/24/26
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