Prosecution Insights
Last updated: July 15, 2026
Application No. 18/176,697

IMAGE DISPLAY DEVICE MANUFACTURING METHOD AND IMAGE DISPLAY DEVICE

Final Rejection §103
Filed
Mar 01, 2023
Priority
Sep 17, 2020 — JP 2020-156726 +2 more
Examiner
OH, JIYOUNG
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
NICHIA Corporation
OA Round
2 (Final)
77%
Grant Probability
Favorable
3-4
OA Rounds
1m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
30 granted / 39 resolved
+8.9% vs TC avg
Strong +24% interview lift
Without
With
+24.5%
Interview Lift
resolved cases with interview
Typical timeline
3y 6m
Avg Prosecution
30 currently pending
Career history
90
Total Applications
across all art units

Statute-Specific Performance

§103
87.6%
+47.6% vs TC avg
§102
6.8%
-33.2% vs TC avg
§112
4.8%
-35.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 39 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Status of the Application Acknowledgement is made of the amendment received on 3/25/2026. Claims 1-23 are pending in this application. Claims 1 and 9 are amended. Claims 11-23 remain withdrawn. Claims 1-10 are presented in this Office Action. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-3 and 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over Saito et al. (US 2016/0240561; hereinafter ‘Saito’) in view of Xu et al. (US 2019/0067525; hereinafter ‘Xu’) and Liu et al. (TW I670546B; hereinafter ‘Liu’). Regarding claim 1, Saito teaches an image display device manufacturing method (the manufacturing of LED display device, [0003]) comprising: preparing (shown in FIG. 1, [0023]) a semiconductor layer (the stacked semiconductor structure including 11, 12, 13, [0024]; hereinafter ‘SL’) comprising a light-emitting layer (13); bonding (shown in FIG. 12, [0109]) the semiconductor layer (SL) to a first surface (the surface facing 11, [0112]) of a light-transmitting substrate (the light-transmitting substrate including 121, 122; 131, 132; 141, 142, [0112]; hereinafter the light-transmitting substrate is referred to as ‘LTS’, and its first surface is referred to as ‘LTSF’); UP’); forming (shown in FIG. 13) a first insulating film (31, 32, and 33 of 30, [0037, 0047, 0115]; hereinafter ‘IF1’), covering the first surface of the light-transmitting substrate (LTSF) and the light-emitting element (10); forming a circuit element (G1, [0050]) on the first insulating film (IF1); forming a second insulating film (36 of 30, [0115]) covering the first insulating film (IF1) and the circuit element (G1); forming a first via (the first via extending vertically from e2, [0028]; hereinafter ‘V1’) the via (V1) passing through the first insulating film (IF1) and the second insulating film (36); and forming a first wiring layer (the first wiring layer is the conductive layer formed on 36, [0054]; hereinafter ‘W1’) on the second insulating film (36), wherein: the first via (IF1) is located between the first wiring layer (W1) and the upper surface of the light-emitting element (10UP), and electrically connects (shown in FIG. 13) the first wiring layer (W1) and the upper surface of the light-emitting element (10UP). Saito does not teach the image display device manufacturing method comprising etching the semiconductor layer on the first surface of the light-transmitting substrate and in a plan view, the circuit element does not overlap the light-emitting element. Xu teaches an image display device manufacturing method [0006] comprising etching (etching, FIG. 2, [0022]) the semiconductor layer (120) on the first surface of the light-transmitting substrate (the surface of 102 facing 120). As taught by Xu, one of ordinary skill in the art would utilize and modify the above teaching into Saito to obtain and achieve the image display device manufacturing method comprising etching the semiconductor layer on the first surface of the light-transmitting substrate as claimed, because it facilitates stable handling of the epitaxial layer and enables subsequent patterning of trenches and through-hole with respect to the final device configuration [0022, 0036]. Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Xu in combination with Saito due to above reason. Saito in view of Xu does not teach the image display device manufacturing method comprising in a plan view, the circuit element does not overlap the light-emitting element. Liu teaches an image display device [0052] comprising in a plan view (FIG. 1), a circuit element does not overlap a light-emitting element (E1 including transistors does not overlap with L1, [0075]). As taught by Liu, one of ordinary skill in the art would utilize and modify the above teaching into Saito in view of Xu to obtain and achieve the image display device manufacturing method comprising in a plan view, the circuit element does not overlap the light-emitting element as claimed, because placing the circuit element between light-emitting elements improves space utilization within the pixel area and reduces the arrangement of lines or electrical elements outside the pixel area [0075]. Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Liu in combination with Saito in view of Xu due to above reason. Regarding claim 2, Saito in view of Xu and Liu teaches the image display device manufacturing method according to claim 1, further comprising: before the step of bonding the semiconductor layer, roughening (Saito: shown in FIG. 3, [0070]) an exposed surface (11a) of the semiconductor layer (SL) to form a roughened surface (11p forms on 11a). Saito in view of Liu does not teach the image display device manufacturing method further comprising forming a film having light transmittance across the exposed surface. Xu teaches the image display device manufacturing method further comprising forming a film (130, FIG. 2, [0022]) having light transmittance (130 is a transparent bonding layer) across the exposed surface (the surface of 120 facing 102). It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Xu to obtain and achieve the image display device manufacturing method further comprising forming a film having light transmittance across the exposed surface as claimed, because providing a bonding film serves to planarize the bonding surface and enhance bonding reliability [0015]. Regarding claim 3, Saito in view of Xu and Liu teaches the image display device manufacturing method according to claim 1, further comprising: forming (Saito: shown in FIG. 13) a second via (the second via extending vertically from e1, [0028]; hereinafter ‘V2’) passing through the first insulating film (IF1) and the second insulating film (36), wherein the light-emitting element (10) comprises a connecting portion (e1), and the second via (V2) is located between and electrically connects (shown in FIG. 13) the first wiring layer (W1) and the connecting portion (e1). Regarding claim 6, Saito in view of Xu and Liu teaches the image display device manufacturing method according to claim 1, further comprising forming a light-blocking layer (Saito: 23, FIG. 5, [0078-0080]) on the first insulating film (IF1). Although, Saito’s FIG.5 does not explicitly teach the image display device manufacturing method comprising before the step of forming the circuit element, forming a light-blocking layer. Saito’s FIG. 13, however, illustrates application of a top-gate transistor configuration. In such a configuration, the light-block layer (23) may be formed prior to formation of the circuit element (G1). It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Saito to obtain and achieve the image display device manufacturing method comprising before the step of forming the circuit element, forming a light-blocking layer as claimed, because the relative position and formation sequence of the gate electrode and the light-blocking layer depend on the selected transistor configuration, which is a well-known design choice in the art [0058, 0115]. Further, it has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70. Regarding claim 7, Saito in view of Xu and Liu teaches the image display device manufacturing method according to claim 1, further comprising: before the step of forming the first insulating film (Saito: IF1, FIG. 13), forming a third wiring layer (e2, [0028]) covering the light-emitting element (e2 covering 10). Regarding claim 8, Saito in view of Xu and Liu teaches the image display device manufacturing method according to claim 1, wherein: the semiconductor layer comprises a gallium nitride compound semiconductor (Saito: SL includes a gallium nitride compound semiconductors, and [0043, 0117]). Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Saito (US 2016/0240561) in view of Xu (US 2019/0067525) and Liu (TW I670546B), and future in view of Hwang et al. (Microelectronic Engineering 77, 71-75, 2005; hereinafter ‘Hwang’). Regarding claim 4, Saito in view of Xu and Liu teaches the image display device manufacturing method according to claim 1, Saito in view of Liu does not teach the image display device manufacturing method further comprising: before the step of bonding the semiconductor layer, forming a conductive layer having light transmittance on the semiconductor layer; and after the step of bonding the semiconductor layer, etching the conductive layer to form a second wiring layer. Xu teaches the image display device manufacturing method further comprising before the step of bonding the semiconductor layer, forming a conductive layer (114 is an N-type ohmic contact layer, FIG. 1, [0021]) on the semiconductor layer (120); and after the step of bonding the semiconductor layer, etching (114 is patterned by lithography, , FIG. 2, [0033]) the conductive layer (114) to form a second wiring layer (114 forms an ohmic contact region of 182, [0022]). It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Xu to obtain and achieve the image display device manufacturing method further comprising: before the step of bonding the semiconductor layer, forming a conductive layer on the semiconductor layer; and after the step of bonding the semiconductor layer, etching the conductive layer to form a second wiring layer as claimed, because it serves as a conductive layer forming part of a conductive path connecting the semiconductor layer and the electrode, thereby facilitating current flow through the device [0021, 0035, 0039]. Saito in view of Xu and Liu does not teach that the N-type ohmic contact layer having light transmittance. Hwang teaches an image display device manufacturing method (1. Introduction) comprising N-type ohmic contact layer (ITO) having light transmittance (ITO is the transparent layer, abstract). As taught by Hwang, one of ordinary skill in the art would utilize and modify the above teaching into Saito in view of Xu and Liu to obtain and achieve the image display device manufacturing method further comprising forming a conductive layer having light transmittance as claimed, because ITO is a known material and widely used for transparent electrode in the art (1. Introduction). Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416. Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Hwang in combination with Saito in view of Xu and Liu due to above reason. Regarding claim 5, Saito in view of Xu, Liu, and Hwang teaches the image display device manufacturing method according to claim 4, further comprising: forming (Saito: shown in FIG. 13) a second via (the second via extending vertically from e1, [0028]; hereinafter ‘V2’) passing through the first insulating film (IF1) and the second insulating film (36), wherein the second via (V2) is located between and electrically connects (shown in FIG. 13) the first wiring layer (W1) and the connection portion (e1). Although, Saito describes the second via as electrically connecting the first wiring layer and a connection portion, the connecting portion of Saito corresponds to an electrode. Xu teaches that the second wiring layer functions as an ohmic contact region of an electrode 182 (FIG. 2, [0021-0022]). It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Saito in view of Xu to obtain and achieve the image display device manufacturing method further comprising the second via is located between and electrically connects the first wiring layer and the second wiring layer as claimed, because the connection portion of Saito and the second wiring layer of Xu are functionally equivalent as electrodes. Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Saito (US 2016/0240561) in view of Xu (US 2019/0067525) and Liu (TW I670546B), and future in view of Shin et al. (US 2018/0308420; hereinafter ‘Shin’). Regarding claim 9, Saito in view of Xu and Liu teaches the image display device manufacturing method according to claim 1, further comprising: forming a wavelength conversion member (Saito: 121, 122, FIG. 12, [0111]). Saito in view of Xu and Liu does not teach the image display device manufacturing method comprising forming a wavelength conversion member on a second surface of the light-transmitting substrate located on a side opposite to the first surface of the light-transmitting substrate. Shin teaches the image display device manufacturing method [0010] further comprising: forming (shown in FIG. 1) a wavelength conversion member (150, 160, and 170, [0049]; hereinafter ‘WCM’) on a second surface of the light-transmitting substrate (the surface of 110 on which WCM is formed, [0037, 0046]) located on a side opposite to the first surface of the light-transmitting substrate (the surface of 110 facing 120). As taught by Shin, one of ordinary skill in the art would utilize and modify the above teaching into Saito in view of Xu and Liu to obtain and achieve the image display device manufacturing method comprising forming a wavelength conversion member on a second surface of the light-transmitting substrate located on a side opposite to the first surface of the light-transmitting substrate as claimed, because it provides a flat and stable surface that facilitates easy application and patterning of the color conversion materials, thereby improving manufacturability [0058]. Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Shin in combination with Saito in view of Xu and Liu due to above reason. Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Saito (US 2016/0240561) in view of Xu (US 2019/0067525) and Liu (TW I670546B), and future in view of Choi et al. (US 2020/0168663; hereinafter ‘Choi’). Regarding claim 10, Saito in view of Xu and Liu teaches the image display device manufacturing method according to claim 1, but does not teach the image display device manufacturing method further comprising: removing the light-transmitting substrate and forming a wavelength conversion member in place of the light-transmitting substrate. Choi teaches the image display device manufacturing method [0002] further comprising: removing (shown in FIG. 16) the light-transmitting substrate (460 is etched to form a window region, [0144]) and forming (shown in FIG. 18) a wavelength conversion member (481, 482, 483, [0146]) in place of the light-transmitting substrate (shown in FIG. 18). As taught by Choi, one of ordinary skill in the art would utilize and modify the above teaching into Saito in view of Xu and Liu to obtain and achieve the image display device manufacturing method further comprising: removing the light-transmitting substrate and forming a wavelength conversion member in place of the light-transmitting substrate as claimed, because removing the light-transmitting substrate creates a direct light-emission window that reduces optical loss and increases light transmission efficiency [0144]. Further the wavelength conversion member is formed on the light-emission side opposite the driving layer to convert light emitted from the active layer into different colors while avoiding interference with the driving circuitry and securing a light-emitting region [0077, 0145]. Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Choi in combination with Saito in view of Xu and Liu due to above reason. Response to Arguments Applicant's arguments with respect to claims have been considered but are moot in view of the new ground of rejection. Response to arguments on newly added limitations are responded to in the above rejection. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JIYOUNG OH whose telephone number is (703)756-5687. The examiner can normally be reached Monday-Friday, 9AM-5PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, EVA MONTALVO can be reached on (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JIYOUNG OH/Examiner, Art Unit 2818 /DUY T NGUYEN/Primary Examiner, Art Unit 2818 4/8/26
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Prosecution Timeline

Mar 01, 2023
Application Filed
Jan 06, 2026
Non-Final Rejection mailed — §103
Mar 25, 2026
Response Filed
Apr 10, 2026
Final Rejection mailed — §103
Jul 09, 2026
Request for Continued Examination
Jul 14, 2026
Response after Non-Final Action

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Prosecution Projections

3-4
Expected OA Rounds
77%
Grant Probability
99%
With Interview (+24.5%)
3y 6m (~1m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 39 resolved cases by this examiner. Grant probability derived from career allowance rate.

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