DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Group I in the reply filed on 11/26/25 is acknowledged.
Applicant's election with traverse of Species 1b, 2a and 3b, corresponding to claims in the reply filed on 11/26/25 is acknowledged. The traversal is on the ground(s) that:
Figures 8 and 9 are not species to each other;
There is no detailed rationale for species;
The embodiments of species 3 can be used with the embodiments of species 1, and the embodiments of species 2 can be used with species 1 and/or 3.
In response to these arguments:
This is found persuasive and as a result figure 9 is removed from species 3;
In species 1, the shapes of the pads are different, as shown in the inset, in species 2, the shapes and locations of the solder interconnects vary, and in species 3, the relative locations of the first and second plurality of pads varies.
It is acknowledged that the three species groups can be used together. There is no constraint on how species 1, 2 and 3 interact, meaning the examined invention is the combination of the three species. Each species is separately restrictable and the examined invention is the combination of the three species.
The resulting elected claims are 1-13 and 18-20.
The requirement is still deemed proper and is therefore made FINAL.
Rejections over Nagai et al., US 8,067,950
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 8 and 9 is/are rejected under 35 U.S.C. 102a as being clearly anticipated by Nagai et al., US 8,067,950.
Regarding claim 1, Nagai (figures 1-2) teaches a device comprising:
an integrated device 10 comprising:
a die substrate 10;
an interconnect portion (12a & 12b) coupled to the die substrate 10,
wherein the interconnect portion (12a & 12b) includes a first plurality of pads 12b and a second plurality of pads 12a,
wherein the first plurality of pads 12b are configured to provide a first plurality of electrical paths for input/output signals, and
wherein the second plurality of pads 12a are configured to provide a second plurality of electrical paths for power;
a passivation layer 13 coupled to the interconnect portion 12a/12b;
wherein the passivation layer 13 comprises a plurality of openings 13a/13b, and wherein the plurality of openings 13a/13b include at least one opening 13b located over a pad from the first plurality of pads 12b; and
a plurality of pillar interconnects 15a/15b coupled to the first plurality of pads 12b and the second plurality of pads 12a.
With respect to claim 2, Nagai (figure 2) teaches there is at least one opening 13a/13b in the passivation layer 13 that is located over each pad 12b from the first plurality of pads 12b.
As to claim 3, Nagai (figure 2) teaches the integrated device further comprises a plurality of solder interconnects 16a/16b coupled to the plurality of pillar interconnects 15a/15b.
In re claim 4, Nagai (figure 1) teaches each pad 12a from the first plurality of pads 12b includes a length that is aligned in a diagonal direction relative to an edge of the integrated device.
Concerning claim 5, Nagai (figure 1) teaches the first plurality of pads 12b are located along a periphery of the integrated device, and wherein the second plurality of pads 12a are laterally surrounded by the first plurality of pads 12b.
Pertaining to claim 8, Nagai (figure 3) teaches a substrate 20 coupled to the integrated device 10 through a plurality of solder interconnects 16a/16b, wherein the plurality of solder interconnects 16a/16b are coupled to the plurality of pillar interconnects 15a/15b (as shown in figure 2).
In claim 9, Nagai (figure 3) teaches a board 20 coupled to the integrated device 10 through a plurality of solder interconnects 16a/16b, wherein the plurality of solder interconnects 16a/16b are coupled to the plurality of pillar interconnects 15a/15b (as shown in figure 2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 6, 7, and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nagai et al., US 8,067,950, as applied to claim 1 above.
Regarding claim 6, Nagai (figure 2) teaches a portion of a surface of a pad 12b from the first plurality of pads 12b is exposed through an opening 13b in the passivation layer 13, is not touching a solder interconnect 16b, but Nagai fails to teach at least one pad 12b from the first plurality of pads 12b has a rectangular shape, an oval shape or an oblong shape.
It would have been obvious to one of ordinary skill in the art at the time of the invention to use one of these shapes in the invention of Nagai because changes in shape are within the ordinary level of skill in the art (MPEP 2144.04 IV).
With respect to claim 7, Nagai (figure 2) teaches a portion of a surface of a pad 12a from the second plurality of pads 12a is exposed through an opening 13a in the passivation layer 13, is not touching a solder interconnect 16a, but Nagai fails to teach at least one pad 12a from the first plurality of pads 12a has a rectangular shape, an oval shape or an oblong shape.
It would have been obvious to one of ordinary skill in the art at the time of the invention to use one of these shapes in the invention of Nagai because changes in shape are within the ordinary level of skill in the art (MPEP 2144.04 IV).
As to claim 10, though Nagai fails to teach the device is selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, and a device in an automotive vehicle, it would have been obvious to one of ordinary skill in the art at the time of the invention to use one of these devices in the invention of Nagai because they are all conventionally known and used devices. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
Claim(s) 11-13 and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nagai et al., US 8,067,950, in view of Jung et al., US 2023/0317532.
In re claim 11, Nagai (figure 2) teaches an integrated device comprising:
a die substrate 10;
an interconnect portion 12a/12b coupled to the die substrate 10,
wherein the interconnect portion 12a/12b includes a first plurality of pads 12b and a second plurality of pads 12a,
wherein the first plurality of pads 12b are configured to provide a first plurality of electrical paths for input/output signals, and
wherein the second plurality of pads 12a are configured to provide a second plurality of electrical paths for power, and
a passivation layer 13 coupled to the interconnect portion 12a/12b,
wherein the passivation layer 13 comprises a plurality of openings 13a/13b.
Nagai fails to teach the plurality of openings include at least two openings located over a pad from the first plurality of pads.
Jung (figure 2) teaches the passivation layer 130/150 comprises a plurality of openings T1-T6, and wherein the plurality of openings T1-T6 include at least two opening T5/T6 located over a pad 103/113/123 from the first plurality of pads 103/113/123; and a plurality of pillar interconnects 140_1 coupled to the first plurality of pads 103/113/123 and the second plurality of pads (pillar 15a connected to pads 12a of Nagai).
It would have been obvious to one of ordinary skill in the art at the time of the invention to use the configuration of Jung in the invention of Nagai because Jung teaches it improves the reliability of the external terminals (paragraph 0003).
Concerning claim 12, Jung (figure 2) teaches there are at least two openings T5/T6 in the passivation layer 130/150 that are located over each pad 103/113/123 & 101/111/121 from the first plurality of pads.
Pertaining to claim 13, Nagai (figure 2) teaches there is one opening 13a in the passivation layer 130/150 that is located over each pad 12a from the second plurality of pads 12a.
In claim 18, Nagai (figure 1) teaches each pad 12b from the first plurality of pads 12b include a length that is aligned in a diagonal direction relative to an edge of the integrated device 10.
Regarding claim 19, Nagai (figure 1) teaches first plurality of pads 12b are located along a periphery of the integrated device 10, and wherein the second plurality of pads 12a are laterally surrounded by the first plurality of pads 12b.
With respect to claim 20, Nagai (figure 1) teaches pads 12b from the first plurality of pads 12b have a different shape than pads 12a from the second plurality of pads 12a.
Rejections over Sun et al., US 2023/0384367
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4, 8-10, 12-13, and 18 is/are rejected under 35 U.S.C. 102(a)(2) as being clearly anticipated by Sun et al., US 2023/0384367.
The applied reference has a common assignee and some common inventors with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
As to claim 1, Sun (figure 7A & marked up figure 2B below) teaches a device comprising:
an integrated device 200 comprising:
a die substrate 210;
an interconnect portion 230 coupled to the die substrate 210,
wherein the interconnect portion 230 includes a first plurality (figure 7A: 732) of pads 1 and a second plurality (figure 7A: 736) of pads 234,
wherein the first plurality (figure 7A: 732) of pads 1 are configured to provide a first plurality of electrical paths for input/output signals, and
wherein the second plurality (figure 7A: 736) of pads 234 are configured to provide a second plurality of electrical paths for power;
a passivation layer 2 coupled to the interconnect portion 230,
wherein the passivation layer 2 comprises a plurality of openings 232/234/3, and wherein the plurality of openings 232/234/3 include at least one opening 3 located over a pad 1 from the first plurality (figure 7A: 732) of pads 1; and
a plurality of pillar interconnects 242 coupled to the first plurality of pads 1 and the second plurality (figure 7A: 736) of pads 234.
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In re claim 2, Sun (see marked up figure 2B above) teaches at least one opening 3 in the passivation layer 2 that is located over each pad from the first plurality (figure 7A: 732) of pads 1.
Concerning claim 3, Sun (see marked up figure 2B above) teaches the integrated device 200 further comprises a plurality of solder interconnects 244 coupled to the plurality of pillar interconnects 242.
Pertaining to claim 4, Sun (figure 7A) teaches each pad 736 from the first plurality of pads 736 includes a length that is aligned in a diagonal direction relative to an edge of the integrated device 700.
In claim 8, Sun (figures 1 and 2B) teaches a substrate 190 coupled to the integrated device 110 through a plurality of solder interconnects 244, wherein the plurality of solder interconnects 244 are coupled to the plurality of pillar interconnects 242.
Regarding claim 9, Sun (figures 1 and 2B) teaches a board 190 coupled to the integrated device 110 through a plurality of solder interconnects 244, wherein the plurality of solder interconnects 244 are coupled to the plurality of pillar interconnects 242.
With respect to claim 10, Sun (paragraph 0096) teaches the device is selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, and a device in an automotive vehicle.
As to claim 11, Sun (figures 7A & marked up figure 2B above) teaches an integrated device comprising:
a die substrate 210;
an interconnect portion 230 coupled to the die substrate 210,
wherein the interconnect portion 230 includes a first plurality of pads 1 and a second plurality of pads 234,
wherein the first plurality (figure 7A:732) of pads 232/234 are configured to provide a first plurality of electrical paths for input/output signals, and
wherein the second plurality (figure 7A:736) of pads 1 are configured to provide a second plurality of electrical paths for power, and
a passivation layer 2 coupled to the interconnect portion 230,
wherein the passivation layer 2 comprises a plurality of openings 232/234/3, and
wherein the plurality of openings 232/234/3 include at least two openings 232/234 located over a pad from the first plurality of pads 232/234.
In re claim 12, Sun (marked up figure 2B above) teaches there are at least two openings 232/234 in the passivation layer 2 that are located over each pad 232/234 from the first plurality of pads 232/234.
Concerning claim 13, Sun (marked up figure 2B above) teachethere is one opening 3 in the passivation layer 2 that is located over each pad from the second plurality of pads 1.
Pertaining to claim 18, Sun (figure 7A) teaches each pad 732/734 from the first plurality of pads 232/234 include a length that is aligned in a diagonal direction relative to an edge of the integrated device 700.
Claim(s) 5-7, 19 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sun et al., US 2023/0384367, as applied to claims 1 and 11 respectively above, and further in view of Nagai et al., US 8,067,950.
In claim 5 and 19, Sun fails to teach the first plurality of pads are located along a periphery of the integrated device, and wherein the second plurality of pads are laterally surrounded by the first plurality of pads.
Nagai (figure 1) teaches the first plurality of pads 12b are located along a periphery of the integrated device, and wherein the second plurality of pads 12a are laterally surrounded by the first plurality of pads 12b.
It would have been obvious to one of ordinary skill in the art at the time of the invention to use the configuration of Nagai in the invention of Sun because Nagai (column 2, line 64-column 3, line 11) teaches this configuration enhances reliability in determining the connection state.
Regarding claim 6, Sun (see marked up figure 2B above) teaches a portion of a surface of a pad 1 from the first plurality of pads 234 is exposed through an opening in the passivation layer 2, is not touching a solder interconnect 244, but even though Sun fails to teach at least one pad from the first plurality of pads has a rectangular shape, an oval shape or an oblong shape, it would have been obvious to one of ordinary skill in the art at the time of the invention to use these shapes in the invention of Sun because changes in shape are within the ordinary level of skill in the art (MPEP 2144.04 IV).
With respect to claim 7, Sun (see marked up figure 2B above) teaches a portion of a surface of a pad 1 from the second plurality of pads 1 is exposed through an opening 3 in the passivation layer 2, is not touching a solder interconnect 244, and though Sun fails to teach at least one pad 1 from the second plurality of pads 1 has a rectangular shape, an oval shape or an oblong shape, it would have been obvious to one of ordinary skill in the art at the time of the invention to use these shapes in the invention of Sun because changes in shape are within the ordinary level of skill in the art (MPEP 2144.04 IV).
As to claim 20, Nagai teaches pads from the first plurality of pads 12a have a different shape than pads from the second plurality of pads 12b.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The cited prior art teaches the concept of a pad with two openings.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID A ZARNEKE whose telephone number is (571)272-1937. The examiner can normally be reached M-F.
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/DAVID A ZARNEKE/ Primary Examiner, Art Unit 2891 2/20/26