Prosecution Insights
Last updated: May 29, 2026
Application No. 18/177,010

SEMICONDUCTOR DEVICE

Non-Final OA §102
Filed
Mar 01, 2023
Priority
Jun 06, 2022 — JP 2022-091833 +1 more
Examiner
YUSHINA, GALINA G
Art Unit
2811
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Kioxia Corporation
OA Round
2 (Non-Final)
79%
Grant Probability
Favorable
2-3
OA Rounds
0m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 79% — above average
79%
Career Allowance Rate
846 granted / 1069 resolved
+11.1% vs TC avg
Strong +17% interview lift
Without
With
+16.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
26 currently pending
Career history
1100
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
72.5%
+32.5% vs TC avg
§102
6.0%
-34.0% vs TC avg
§112
19.1%
-20.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1069 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Acknowledgement of RCE Filing A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed 03/31/26 has been entered. The amendment filed on 03/31/26 has been entered. Applicant did not amend Claims, but provided a new IDS that has been considered. Status of Claims Since the Applicant did not amend claims, a set of claims for examination includes Claims 1-3, 5-15, and 17-18 as filed 01/22/26, with Claims 4, 16, and 19-20 cancelled by the Applicant and Claims 6-11 withdrawn from examination as of 01/22/26, but rejoined with allowed Claim 1 in the Notice of Allowability mailed 03/05/26. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim 12 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Utsumi (US 2018/0047744). In re Claim 12, Utsumi teaches a semiconductor device comprising (Fig. 1 and Annotated Fig. 1) Annotated Fig. 1 PNG media_image1.png 400 661 media_image1.png Greyscale a substrate 10 (paragraph 0045); a stack of films 30 (paragraph 0045) disposed above the substrate 10 and including a plurality of electrode layers separated from each other in a first direction Z; an array region – within region 30b (paragraphs 0051, 0057-0062) disposed on the substrate 10 and including a memory cell array (paragraph 0004), the memory cell array having a plurality of word lines WL and a plurality of select lines SGS, SGD (paragraph 0050) that constitute the plurality of electrode layers; a first plug region – in region 30a – at a border with region 30b - disposed on the substrate 10, located in the second direction (“-x”) of the array region, and including a first contact plug FCP (FCP is similar to plug 47, but is not being a bit line) electrically connected to a first select line SGD; and a second plug region – around “SCP” (as identified in Annotated Fig. 1) - disposed on the substrate 10 in the second direction of the first plug region, and including a second contact plug SCP electrically connected to a first word line – being the top WL 32 - of the plurality of word lines (see 0055-0056 on electrical conductivity of 33a), wherein the plurality of electrode layers includes a first electrode layer, the first electrode layer including the first word line – the top WL 32- and the second contact plug SCP penetrates an electrode layer (one of multiple electrode layers under the upper WL 32 - provided between the substrate 10 and the first electrode layer – the upper WL 32. Allowable Subject Matter Claims 1-3, 5-11, 13-15, and 17-18 are allowed. Reason for Identification of Allowable Subject Matter The following is an Examiner Statement of Reasons for Allowance: Re Claim 1: The prior arts of record, alone or in combination, fail(s) to anticipate or render obvious such limitation as: “a plurality of second insulating films disposed in the stack of films and each second insulating film having a portion extending between corresponding two of the first insulating films”, in combination with other limitations of the claim. Re Claim 13: The prior arts of record, alone or in combination, fail(s) to anticipate or render obvious such limitation as: “a plurality of second insulating films disposed in the stack of films and each second insulating film having a portion extending between corresponding two of the first insulating films”, in combination with other limitations of the claim. Re Claims 2-3, 5-11, 14-15, and 17-18: Claims 2-3, 5-11, 14-15, and 17-18 are allowed due to dependency either on Claim 1 or on Claim 13. The prior arts of record include: Utsumi (US 2018/0047744), Park et al. (US 2014/0306279), Kim et al. (US 20210265389), Yun et al. (US 2021/0118861), Matsumura et al. (US 2021/0313246), Hu et al. (US 2022/0181347), Oike (US 2020/0321350), Hatano et al. (US 2017/0103995), and Baek et al. (US 2019/0237477). Conclusion Any inquiry concerning this communication should be directed to GALINA G YUSHINA whose telephone number is 571-270-7440. The Examiner can normally be reached between 8 AM - 7 PM Pacific Time (Flexible). Examiner interviews are available. To schedule an interview, Applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s Supervisor, Lynne Gurley can be reached on 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300; a fax phone number of Galina Yushina is 571-270-8440. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center - for more information about Patent Center and visit https://www.uspto.gov/patents/docx - for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /GALINA G YUSHINA/Primary Patent Examiner, Art Unit 2811, TC 2800, United States Patent and Trademark Office E-mail: galina.yushina@USPTO.gov Phone: 571-270-7440 Date: 04/07/26
Read full office action

Prosecution Timeline

Show 1 earlier event
Oct 07, 2025
Non-Final Rejection mailed — §102
Jan 22, 2026
Response Filed
Mar 13, 2026
Examiner Interview Summary
Mar 13, 2026
Response after Non-Final Action
Mar 13, 2026
Examiner Interview (Telephonic)
Mar 31, 2026
Request for Continued Examination
Apr 06, 2026
Response after Non-Final Action
Apr 09, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12626762
MEMORY DEVICE STRUCTURE AND FABRICATION METHOD
3y 4m to grant Granted May 12, 2026
Patent 12613423
ILLUMINATION UNIT, METHOD FOR PRODUCING AN ILLUMINATION UNIT, CONVERTER ELEMENT FOR AN OPTOELECTRONIC COMPONENT, RADIATION SOURCE INLCUDING AN LED AND A CONVERTER ELEMENT, OUTCOUPLING STRUCTURE, AND OPTOELECTRONIC DEVICE
4y 5m to grant Granted Apr 28, 2026
Patent 12615797
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
3y 4m to grant Granted Apr 28, 2026
Patent 12615831
SEMICONDUCTOR DEVICE
2y 10m to grant Granted Apr 28, 2026
Patent 12604729
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3y 5m to grant Granted Apr 14, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

2-3
Expected OA Rounds
79%
Grant Probability
96%
With Interview (+16.9%)
2y 4m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 1069 resolved cases by this examiner. Grant probability derived from career allowance rate.

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