Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 13-18 and 20 objected to because of the following informalities: it appears that the claims are mistakenly dependent upon method claim 1.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 19-20 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by McConaghy et al. [US 2009/0228846 A1].
As per claim 19, a computer system [0053] comprising: one or more processors [0133];
a user interface executing on the one or more processors [0069-0070 user interface];
a plurality of analog functional circuit components [0003 analog, 0038 block specific tools including analog], displayed in the user interface [0114 devices in the schematic], comprising a plurality of functional circuit component parameters configured with functional circuit component parameter values [0003 multi-parameter designs (MPDs), selecting parameters], the analog functional circuit components having associated behavioral model parameter values selected from a plurality of behavioral model parameter values based on the functional circuit component parameter values [0094 behavioral models for sub-blocks which are parameterized];
a generator [0073 group of modules] to receive the functional circuit component parameter values for the plurality of analog functional circuit components in the user interface [0073 receive feedback from the group of modules through the display module] and produce a circuit specification for a transistor level schematic comprising a plurality of transistor level functional circuit component schematics corresponding to the plurality of analog functional circuit components [0073 final output of the system can include one or more sized designs, 0082 top down-or bottom up, 0089 models obtained, thorough and rapid exploration of the design variables space, 0095 the goal of getting good final design, 0100 analog designers almost always aim for 100% yield].
20. The computer system of claim 1 wherein the behavioral model parameter values associated with the analog functional circuit components are from one of:
simulated parameters of the transistor level functional circuit component schematics corresponding to the plurality of analog functional circuit components [0076simulation module], or
measured parameters of corresponding functional circuit components in a physical analog circuit [0076 means of measurement].
Claims 19-20 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Walker [US 2013/0311152 A1].
As per claim 19, a computer system comprising:
one or more processors [FIG. 2 element 270, 0035];
a user interface executing on the one or more processors [FIG. 2 element 240, FIG. 3 GUI];
a plurality of analog functional circuit components [0015 circuit components, 0016 the first and second circuits may be analog circuits], displayed in the user interface [0039 menu], comprising a plurality of functional circuit component parameters configured with functional circuit component parameter values [0018 parameterized, values for parameters], the analog functional circuit components having associated behavioral model parameter values selected from a plurality of behavioral model parameter values based on the functional circuit component parameter values [0013 parameterized HDL model, 0018 HDL model for an analog circuit may be parameterized];
a generator [0032 model constructor, 0035 the processor] to receive the functional circuit component parameter values for the plurality of analog functional circuit components in the user interface [0011, 0035] and produce a circuit specification [0033 validation] for a transistor level schematic [0019] transistor level, schematic format] comprising a plurality of transistor level functional circuit component schematics corresponding to the plurality of analog functional circuit components [0032 modeling the behavior may provide a manner for design verification, 0033 validation, transistor level, schematic format].
20. The computer system of claim 1 wherein the behavioral model parameter values associated with the analog functional circuit components are from one of:
simulated parameters of the transistor level functional circuit component schematics corresponding to the plurality of analog functional circuit components [0019 simulation information], or
measured parameters of corresponding functional circuit components in a physical analog circuit [0019 value measurement locations].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 8-14 and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Walker [US 2013/0311152 A1].
Taking claim 1 as exemplary of claims 1 and 12 [FIG. 2, 0061-0063], Walker teaches a computer-implemented method comprising:
storing a plurality of behavioral models [0013 model database that includes parameterized HDL models, 0024 database may be configured to store a parameterized HDL model for each of one or more types of analog circuits, 0046 stored in a database],
wherein particular behavioral models correspond to one or more transistor level schematics produced from a parameterized analog functional circuit component [0019 values for parameters of an instance of an analog circuit, transistor level, schematic format]; and
wherein the behavioral models comprise behavioral model parameters having behavioral model parameter values [0018 parameterized HDL model based on behavior] from one of:
simulated parameters of one of said transistor level schematics [0049 simulation information], or measured parameters of a physical analog circuit produced from one of said transistor level schematics [0049 value measurement locations],
specifying functional circuit component parameter values for a plurality of functional circuit component parameters of said parameterized analog functional circuit component [0046 equations and logic relations between the parameters and how the different parameters affect the behavior of the analog circuit may be established in the parameterized HDL model, 0056 a second value to a second parameter, for each group of related parameters], wherein different functional circuit component parameter values are used to generate a plurality of different transistor level schematics of the parameterized analog functional circuit component [0021 generate values for different parameters, 0033 transistor level, schematic format, 0046 values of parameters used to fully characterize the analog circuit, how the different parameters affect the behavior of the analog circuit may be established in the parameterized HDL model]; and
generating, based on the specified functional circuit component parameter values, a behavioral model of the plurality of behavioral models [0051 generate a behavioral HDL model, 0056 the behavioral hardware description language model may be generated based on the values (plural)].
However, Walker does not appear to teach “selecting” a behavioral model. Yet, the reference is replete with the function of selecting, particularly with respect to type of analog circuit [0027], the selected parameterized HDL model [0029], for the type of analog circuit selected a corresponding parameterized HDL may be selected [0036] for the resultant behavioral model [0036 a behavioral model may also be generated based on the generated values and the selected parameterized HDL model]. Thus, given a broadest reasonable interpretation of the claimed invention, generating could be interpreted as a form of selecting for the specified functional circuit component parameter values for which the generated behavioral model is based upon. Therefore, the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains because the behavioral HDL model may be used by electronic design automation software to model the behavior of the instantiated analog circuit as well as the behavior of a system, which may provide a manner for design verification of the system [0032], which may reduce costs and the time to finalize the circuit design [0002].
As per claim 2, further comprising executing a behavioral simulation of the parameterized analog functional circuit component using the selected behavioral model [0013 may be used by circuit design verification software, 0032 may provide a manner for design verification, 0033 validate a behavioral HDL model].
As per claims 3 and 13, wherein different behavioral models are selected when different functional circuit component parameter values are specified for at least one parameter of the plurality of functional circuit component parameters [0018 how different parameters affect the behavior may be established, parameterized HDL models may be formed based on the operation and behavior of the analog circuits that they model, 0021 generate values for different parameters].
As per claims 4 and 14, wherein a same behavioral model is selected, and different behavioral model parameter values are used in the same behavioral model, when different functional circuit component parameter values are specified for at least one parameter of the plurality of functional circuit component parameters [0018 how different parameters affect the behavior may be established, parameterized HDL models may be formed based on the operation and behavior of the analog circuits that they model, 0021 generate values for different parameters, at the same time].
As per claims 8 and 16, wherein one or more of the plurality of stored behavioral models comprise a plurality of ideal circuit components on a user interface pallet configured to model a functional circuit component having one or more particular parameters [0017 HDL model may contain equations and other logic relations, 0018 equations and logic relations between parameters and how different parameters affect behavior of the analog circuit may be established int eh parameterized HDL model, 0038 GUI, schematic representation, 0039 menu].
As per claims 9 and 17, wherein the behavioral models comprise behavioral model parameters having behavioral model parameter values from the simulated parameters of one of said transistor level schematics [0049 simulation information].
As per claims 10 and 18, wherein the behavioral models comprise behavioral model parameters having behavioral model parameter values from the measured parameters of the physical analog circuit produced from one of said transistor level schematics [0049 value measurement locations].
As per claim 11, wherein the behavioral models comprise behavioral model parameters having a plurality of behavioral model parameter values substantially matching at least a portion of (i) the simulated parameters of one of said transistor level schematics, and (ii) corresponding measured parameters of a physical analog circuit produced from the one of said transistor level schematics [0013 parameterized HDL models, 0019, 0049].
Claims 5-7 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Walker [US 2013/0311152 A1] as applied to claims 1 and 12 above, and further in view of Cadence [“Creating Analog Behavioral Models”].
As per claims 5 and 15, Walker teaches a model may contain statements [0017]. However, Walker does not specifically teach condition statements. Cadence teaches analog behavior modeling provides conditional statements [section 3.5]. Thus, one or more of the plurality of stored behavioral models comprise at least one condition statement based on at least one of the functional circuit component parameters would result by combining these teachings. The claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains because to learn the basics and to reuse and adapt previously written models is not difficult, a designer can extend a set of design aids tremendously with modeling [page 2, section 2, last paragraph].
As per claim 6, wherein the at least one condition statement assigns one or more first behavioral model parameter values to one or more corresponding first behavioral model parameters when at least a first functional circuit component parameter has a first functional circuit component parameter value, and the at least one condition statement assigns one or more second behavioral model parameter values, different than the one or more first behavioral model parameter values, to the one or more corresponding first behavioral model parameters when the first functional circuit component parameter has a second functional circuit component parameter value [Walker, see above for similarly cited limitations, combined with Cadence].
As per claim 7, wherein the at least one condition statement assigns one or more first behavioral model parameter values to one or more corresponding first behavioral model parameters when at least a first functional circuit component parameter has a first functional circuit component parameter value, and the at least one condition statement assigns one or more second behavioral model parameter values to one or more corresponding second behavioral model parameters when the first functional circuit component parameter has a second functional circuit component parameter value [Walker, see above for similarly cited limitations, combined with Cadence].
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See Chang et al. [US 2011/0054875 A1] (entire document); Abbas et al. [US 12,164,850 B2] at FIG. 4A, column 7, line 58-column 8, line 26; Chawda et al. [US 11,138,358 B2] at FIG. 3-5 and 7-9; Kuo et al. [US 2018/0150577 A1] at Abstract, [0027]; Boshart et al. [US 2012/0304140 A1] at Abstract; James et al. [US 2017/0316137 A1] (entire document); Al-Hawari et al. [US 8,452,582 B1] at Abstract; Sokar et al. [US 11,182,525 B1] (entire document); C.F. Gilbert et al. ["Integrated Interactive Modeling of Plasma Opening Stitches Radiation Sources and Bremsstrahlung Diodes with Commercial Circuit Analysis Software Tools"] at section III. Model Creation (pages 256-257).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LEIGH M GARBOWSKI whose telephone number is (571)272-1893. The examiner can normally be reached M-F 9-5 EST.
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/LEIGH M GARBOWSKI/Primary Examiner, Art Unit 2851