DETAILED ACTION
Notice of Pre-AIA or AIA Status
This application, 18/177,087, attorney docket AD9667-US, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This application is assigned to Intel Inc, and has an effective filing date of 09/03/2020 based on provisional application 63074410. Applicant's election without traverse of Group I, claims 1-17 in the reply filed on 11/6/2025 is acknowledged. Claims 18-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Claims 1-17 are pending and are considered below. Note that examiner will use numbers in parentheses to indicate numbered elements in prior art figures, and brackets to point to paragraph numbers where quoted material or specific teachings can be found.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 3 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 3 recites, “the first dielectric layer and the second dielectric layer surrounding the second electrode” it is not clear whether each layer must surround the electrode, or only a combination of the first and second dielectric must surround the electrode.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-17 are rejected under 35 U.S.C. 103 as being unpatentable over Ito et al. (U.S. 6,057,572) in view of Abe et al. (U.S. 2016/0260795).
As for claim 1,
Ito teaches a capacitor structure in figure 3, comprising:
a substrate (20);
a first electrode (7) in the substrate;
a second electrode (12/14/15) over the substrate; But does not teach a third electrode over the second electrode, the third electrode having a middle portion over the second electrode and end portions laterally adjacent to the second electrode.
However, Abe teaches in figure 2, a third electrode (CE3) over the second electrode (shown as CE2), the third electrode having a middle portion over the second electrode and end portions laterally adjacent to the second electrode.
It would have been obvious to one skilled in the art at the effective filing date of this application add the third electrode of Abe to the device of Ito to improve capacitance per unit area. Abe [0015]. One skilled in the art would have combined these elements with a reasonable expectation of success.
As for claim 2,
Ito in view of Abe makes obvious the capacitor structure of claim 1, and in the suggested combination, Abe teaches that the first electrode and the third electrode are at the same electrical potential.(shown in figure 3B).
As for claim 3,
Ito in view of Abe makes obvious the capacitor structure of claim 1, and in the suggested combination Abe teaches a first dielectric layer (CZ1) and a second dielectric layer (CZ2) over the substrate, the first dielectric layer and the second dielectric layer surrounding the second electrode. Shown in figure 2.
As for claim 4,
Ito in view of Abe makes obvious the capacitor structure of claim 3, and in the suggested combination Abe teaches the first dielectric layer is between the first electrode and the second electrode, and the second dielectric layer is between the second electrode and the third electrode.(shown in figure 2)
As for claim 5,
Ito in view of Abe makes obvious the capacitor structure of claim 4, and in the suggested combination Abe teaches the second dielectric layer comprises an end portion on the substrate, and the end portion separates the third electrode from the substrate. (CZ2 extends across the substrate from the ends of CZ1 separating CE3 from the substrate)
As for claim 6,
Ito in view of Abe makes obvious the capacitor structure of claim 3, but the suggested combination does not teach that the first dielectric layer has a first thickness, the second dielectric layer has a second thickness, and the first thickness is thinner than the second thickness.
However, Insulation thickness in a capacitor is a result dependent variable that determines the capacitance and is adjusted to minimize leakage. The upper dielectric deposited around a corner which may require additional thickness to prevent voids at the corner while the oxide is grown and also serves as a gate oxide for the transistors of Abe, so may require less thickness. It would have been obvious to one of ordinary skill in the art, at the time of invention, to optimize the thicknesses and arrive at the claim limitation.
As for claim 7,
Ito in view of Abe makes obvious the capacitor structure of claim 1, and in the suggested combination, Ito teaches that the first electrode is a doped region in the substrate. [co5 ln10+].
As for claim 8,
Ito in view of Abe makes obvious the capacitor structure of claim 1, and in the suggested combination, Abe teaches a fourth electrode over the substrate, the fourth electrode is under the third electrode and laterally adjacent to the second electrode. The third electrode becomes (CE4), which has two portions on the right side adjacent to the CE3, which in the instant claim maps to the fourth electrode, and is adjacent to the second electrode)
As for claim 9,
Ito in view of Abe makes obvious the capacitor structure of claim 8, and in the suggested combination Abe teaches that the fourth electrode is at the same electrical potential as the second electrode. (Voltage potentials V1 and V2 are shown in figure 3B),
As for claim 10,
Ito in view of Abe makes obvious the capacitor structure of claim 8, and in the suggested combination, Abe teaches that a portion of the third electrode is between the second electrode and the fourth electrode. (shown in figure 2 with the mapping suggested in claim 8.)
As for claim 11,
Ito in view of Abe makes obvious the capacitor structure of claim 1, but the combination does not teach that the second electrode includes a trench in an upper portion of the second electrode.
However, Abe teaches in the embodiment of claim 15a, a second electrode (CE3) includes a trench in an upper portion of the second electrode.
It would have been obvious to one skilled in the art at the effective filing date of this application form the trenches in the second electrode of Abe to increase the capacitance value of the device Abe [0199]). One skilled in the art would have combined these elements with a reasonable expectation of success.
As for claim 12,
Ito teaches a capacitor structure in figure , comprising
a substrate (20);
a first capacitor, the first capacitor comprises a first electrode (7) in the substrate and a second electrode (12/14/15) over the substrate; and
but does not teach a second capacitor, the second capacitor comprises the second electrode and a third electrode over the second electrode,
the third electrode having a middle portion over the second electrode and end portions laterally adjacent to the second electrode.
However, Abe teaches in figure 2, and 3B, a second capacitor, the second capacitor comprises the second electrode and a third electrode (CE3) over the second electrode,
the third electrode having a middle portion over the second electrode and end portions laterally adjacent to the second electrode.(shown in figure 2).
It would have been obvious to one skilled in the art at the effective filing date of this application add the third electrode of Abe to the device of Ito to improve capacitance per unit area. Abe [0015]. One skilled in the art would have combined these elements with a reasonable expectation of success.
and Ito makes obvious that the the first electrode, the second electrode, and the third electrode include dopants of the same conductivity. The first and second taught by Ito are both p-dope Si.{co5 ln10+]; and it would be obvious to form the third electrode taught by Abe of the same material to simplify the manufacturing process.
As for claim 13,
Ito in view of Abe makes obvious the capacitor structure of claim 12, and in the suggested combination Ito makes obvious that the first electrode has a first dopant concentration, the second electrode has a second dopant concentration, and the first dopant concentration is at most as high as the second dopant concentration. (in the combination, the materials are the same including the dopant concentration, which provides consistent conductivity in the electrodes.)
As for claim 14,
Ito in view of Abe makes obvious the capacitor structure of claim 13 and in the suggested combination Ito teaches a conductive well (1 ) in the substrate, wherein the first electrode is in the conductive well.
As for claim 15,
Ito in view of Abe makes obvious the capacitor structure of claim 14, but does not teach that the conductive well includes dopants having the same conductivity as the first electrode.
However, Abe teaches that the conductive well (AR42) includes dopants having the same conductivity as the first electrode. (both the electrode and well are formed together).
It would have been obvious to one skilled in the art at the effective filing date of this application to form a conductive will in the isolation well so the lower electrode can be connected laterally away from the electrode on the same side of the substrate One skilled in the art would have combined these elements with a reasonable expectation of success.
As for claim 16,
Ito in view of Abe makes obvious the capacitor structure of claim 15, and in the combination suggested in claim 15, Abe teaches diffusion regions (under isolation 2ir) laterally adjacent to the first electrode in the conductive well, the diffusion regions include dopants having the same conductivity as the conductivity well.
As for claim 17,
Ito in view of Abe makes obvious the capacitor structure of claim 16, and Abe makes obvious that the diffusion regions have a third dopant concentration, and the third dopant concentration is substantially similar to the second dopant concentration. (the regions are formed at the same time, and have substantially the same dopant concentration.)
Conclusion
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/JOHN A BODNAR/ Primary Examiner, Art Unit 2893