DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims presented have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1,2, 5-9 and 15 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Lee et al. (US10204919B2; hereinafter Lee’919).
Regarding claim 1, Fig.5 of Lee’919 teaches a memory device, comprising:
a substrate 101 (col.6, line 52) comprising a memory array region CA (col.6, line 52) and a staircase region CT (col.6, lines 52-53);
a stacked structure GS (col.6, line 48) located on the substrate 101 in the memory array region CA and the staircase region CT, wherein the stacked structure GS comprises a plurality of conductive layers 132a/132b (col.6, lines 49-50) and a plurality of insulating layers 123a/123b (col.6, lines 58-59) stacked alternately;
a separation wall (see annotated Fig.5) extending through the stacked structure GS to divide the stacked structure GS into a first block (see annotated Fig.5) and a second block (see annotated Fig.5);
a plurality of first through vias 171a (col.10, line 27) located in the first block of the staircase region CT, wherein the plurality of first through vias 171a (col.10, line 27) are arranged along a first direction (wherein first contact plugs 171a are arranged along X-direction; x-direction being first direction);
a plurality of second through vias 171b (col.10, lines 27-28) located in the second block of the staircase region CT and adjacent to the first through vias 171a,
wherein a number of layers of the stacked structure GS penetrated by the first through vias 171a is smaller than a number of layers of the stacked structure GS penetrated by the second through vias 171b,
wherein the separation wall extends along the first direction (see annotated Fig.5; separation wall is in x-direction; x-direction being first direction).
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Regarding claim 2, Lee’919 further teaches the memory device according to claim 1, wherein the first through vias 171a (col.10, line 27) are landed on and electrically connected to an interconnection structure on a substrate 101 (col.6, line 52), and the second through vias 171b (col.10, lines 27-28) are landed on and electrically isolated from the interconnection structure
Regarding claim 5, Fig.5 of Lee’919 teaches a memory device, comprising:
a substrate 101 (col.6, line 52) comprising a memory array region CA (col.6, line 52) and a staircase region CT (col.6, lines 52-53);
a memory array CA (col.6, line 52) located in the memory array region CA;
a staircase structure CT (col.6, lines 52-53) located on the substrate 101 in the staircase region CT, wherein the staircase structure CT comprises a recess region (wherein recess region is located on the first block region) and a non-recess region (wherein non-recess region is located on the second block region), wherein a height of a top surface of the recess region is lower than a height of a top surface of the non-recess region (see annotated Fig.5);
first through vias 171a (col.10, line 27) located in the recess region (see annotated Fig.5), wherein the first through vias 171a are arranged along a first direction (wherein first contact plugs 171a are arranged along X-direction; x-direction being first direction); and
a separation wall (see annotated Fig.5) extending through the staircase structure and dividing the staircase structure into a first block (see annotated Fig.5) and a second block (see annotated Fig.5), wherein the separation wall extends along the first direction (see annotated Fig.5; separation wall is in x-direction; x-direction being first direction).
Regarding claim 6, Lee’919 further teaches the memory device according to claim 5, wherein the recess region (see annotated Fig.5) is located in a part of steps of the staircase structure CT (col.6, lines 52-53).
Regarding claim 7, Lee’919 further teaches the memory device according to claim 5, wherein the recess region (see annotated Fig.5) is located in a high step, a middle step, a low step or a combination thereof of the staircase structure CT (col.6, lines 52-53).
Regarding claim 8, Lee’919 further teaches the memory device according to claim 5, wherein the recess region (see annotated Fig.5) extends from a high step to a low step of the staircase structure CT (col.6, lines 52-53).
Regarding claim 9, Lee’919 further teaches the memory device according to claim 5, wherein the staircase structure comprises:
a first stepped portion located in the recess region (see annotated Fig.5); and
a second stepped portion located in the non-recess region (see annotated Fig.5), wherein a height of the first stepped portion is lower than a height of the second stepped portion (see annotated Fig.5), and a length of the first stepped portion is shorter than a length of the second stepped portion.
Regarding claim 15, Lee’919 further teaches the memory device according to claim 5, wherein the recess region (see annotated Fig.5) is located in the first block (see annotated Fig.5), and the non-recess region (see annotated Fig.5) is located in the second block (see annotated Fig.5).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3,4 and 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US10204919B2; hereinafter Lee’919) in view of Shimizu et al. (US9786680B2).
Regarding claim 3, Lee’919 does not teach wherein the memory device further comprising a plurality of contacts located in the second block of the staircase region and landed on the conductive layers.
Fig.4 of Shimizu teaches a semiconductor device that includes electrode films 17 and insulative silicon oxide films 16 are stacked alternately along the Z-direction and contacts 35 that extend in the Z-direction and pierce the insulating film 29 and the inter-layer insulating film 28 are provided; wherein lower end of the contact 35 is connected to the electrode film 17 included in each of the terraces T (col.4, lines 14-16, col.5, lines 57-58).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the contacts 35 of Shimizu in the teachings of Lee’919 in order to provide electrical connection between interconnects 36 and electrode films 17.
Regarding claim 4, Lee’919 does not teach wherein a diameter of the first through vias is greater than a diameter of the second through vias. There is no evidence showing the criticality of the claimed difference in diameters of the first through vias and the second through vias.
The semiconductor art well recognizes that larger diameter of through- hole vias compared to smaller diameters controls parameters critical for device performance, including resistance (resistivity, length and cross-sectional area) and mechanical viability (which includes mechanical strength as imparted by conductor thickness). Shimizu discloses, in annotated Fig.4 and col.6, lines 31-39, wherein the conductive pillars 41 that extend in the Z-direction can be formed by utilizing the stacked body 15n that is formed in the same process as the stacked body 15 for arranging the memory cell transistors along the Z-direction. Thereby, because the greater part of the current path extends in the Z-direction, the resistance element Er that has a high resistance value per unit surface area in the XY plane can be realized. As shown in annotated Fig.4, each of the second through vias has smaller diameter compared to each of the first through vias, and thus higher resistance. The diameter of the first and second through vias is therefore an art recognized result affecting parameter.
According to well established patent law precedents (see, for example, M.P.E.P. § 2144.05), therefore, it would have been obvious to determine (for example by routine experimentation) the optimum difference in diameters of the first through vias and the second through vias.
Annotated Fig.4
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Regarding claim 10, Lee’919 teaches the memory device according to claim 9, wherein
the first through vias 171a (col.10, line 27) extend through the first stepped portion (see annotated Fig.5); and
second through vias 171b (col.10, lines 27-28) extend through the second stepped portion (see annotated Fig.5),
Lee’919 does not teach wherein a diameter of the first through vias is greater than a diameter of the second through vias. There is no evidence showing the criticality of the claimed difference in diameters of the first through vias and the second through vias.
The semiconductor art well recognizes that larger diameter of through- hole vias compared to smaller diameters controls parameters critical for device performance, including resistance (resistivity, length and cross-sectional area) and mechanical viability (which includes mechanical strength as imparted by conductor thickness). Shimizu discloses, in annotated Fig.4 and col.6, lines 31-39, wherein the conductive pillars 41 that extend in the Z-direction can be formed by utilizing the stacked body 15n that is formed in the same process as the stacked body 15 for arranging the memory cell transistors along the Z-direction. Thereby, because the greater part of the current path extends in the Z-direction, the resistance element Er that has a high resistance value per unit surface area in the XY plane can be realized. As shown in annotated Fig.4, each of the second through vias has smaller diameter compared to each of the first through vias, and thus higher resistance. The diameter of the first and second through vias is therefore an art recognized result affecting parameter.
According to well established patent law precedents (see, for example, M.P.E.P. § 2144.05), therefore, it would have been obvious to determine (for example by routine experimentation) the optimum difference in diameters of the first through vias and the
second through vias.
Regarding Fig.11, Shimizu further teaches the memory device according to claim 10, further comprising: contacts landed on the second stepped portion and adjacent to the second through vias (see Annotated Fig.4).
Regarding Fig.12, Shimizu further teaches the memory device according to claim 9, wherein the first through vias extend through the first stepped portion of the staircase structure; and
there is no through via extending through the second stepped portion (see Annotated Fig.4).
Claims 14,16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable Lee et al. (US10204919B2; hereinafter Lee’919) in view of Lee et al. (US10043818B2; hereinafter Lee’818).
Regarding claim 14, Lee’919 does not teach wherein the recess region and the non-recess region are located in the first block.
Fig.7 of Lee’818 teaches a semiconductor device that includes first and second stacks of electrodes and wherein the semiconductor includes a first pad region P1 and a second pad region P2; wherein the first pad region P1 is a recess region and second pad region P2 being non-recess region and wherein the first pad region P1 and the second pad region P2 are located in the same block.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the first pad region P1 is a recess region and second pad region P2 being non-recess region of Lee’818 in the teachings of Lee’919 in order to form a single stair shape in the second direction D2 (Lee’818, [col.8, lines 50-51]).
Regarding claim 16, Lee’919 does not teach wherein the recess region comprises first recesses and second recesses staggered with each other, and respectively located at opposite sides of the memory array region of the substrate.
Fig.7 of Lee’818 teaches a semiconductor device that includes first and second stacks of electrodes and wherein the semiconductor includes a first pad region P1 and a second pad region P2; wherein the first pad region P1 is a recess region and second pad region P2 being non-recess region; and wherein there’s first pad region P1 in first stack ST1 and another first pad region P1 in second stack ST2 (col.7, lines 49-51).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the first pad region of Lee’818 in the teachings of Lee’919 in order to accommodate the height of the first contacts MC1.
Regarding claim 17, Lee’818 further teaches the memory device according to claim 5, wherein adjacent recesses P1 (col.8, lines 46-51) of two adjacent tiles are staggered with each other.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINCENT KIPKEMOI RONO whose telephone number is (571)270-5977. The examiner can normally be reached Mon-Fri, 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571)272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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VINCENT KIPKEMOI. RONO
Examiner
Art Unit 2891
/V.K.R./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
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