DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Group I in the reply filed on 08/25/2025 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim 18-20 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected group, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 08/25/2025.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 5-9 and 12 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Freeman et al. (US20150214107A1).
Regarding claim 5, Fig.10 of Freeman teaches a memory device, comprising: a substrate (para.0025) comprising a memory array region 122 (para.0027) and a staircase region 124 (para.0027); a memory array located in the memory array region 122 (para.0027); a staircase structure 100 (para.0025) located on the substrate (para.0025) in the staircase region 124, wherein the staircase structure 100 comprises a recess region (see annotated Fig.10) and a non-recess region (see annotated Fig.10), wherein a height of a top surface of the recess region (see annotated Fig.10) is lower than a height of a top surface of the non-recess region (see annotated Fig.10); and first through vias 120 (para.0040) located in the recess region.
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Regarding claim 6, Fig.10 of Freeman further teaches the memory device according to claim 5, wherein the recess region (see annotated Fig.10) is located in a part of steps of the staircase structure 100 (para.0025).
Regarding claim 7, Fig.10 of Freeman further teaches the memory device according to claim 5, wherein the recess region (see annotated Fig.10) is located in a high step, a middle step, a low step or a combination thereof of the staircase structure 100 (para.0025).
Regarding claim 8, Fig.10 of Freeman further teaches the memory device according to claim 5, wherein the recess region (see annotated Fig.10) extends from a high step to a low step of the staircase structure 100 (para.0025).
Regarding claim 9, Fig.10 of Freeman further teaches wherein the memory device according to claim 5, wherein the staircase structure 100 (para.0025) comprises: a first stepped portion (see annotated Fig.10) located in the recess region (see annotated Fig.10); and a second stepped portion (see annotated Fig.10) located in the non-recess region (see annotated Fig.10), wherein a height of the first stepped portion is lower than a height of the second stepped portion (see annotated Fig.10), and a length of the first stepped portion is shorter than a length of the second stepped portion (see annotated Fig.10).
Regarding claim 12, Freeman further teaches the memory device according to claim 9, wherein the first through vias 120 (para.0041, wherein the conductive contacts 120 may be formed to extend from each conductive material 112 through the stair-step structure 100 to the substrate) extend through the first stepped portion (see annotated Fig.10) of the staircase structure 100 (para.0025); and there is no through via extending through the second stepped portion (see annotated Fig.10).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3,13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Freeman et al. (US20150214107A1) in view of SIM et al. (US20210036010A1).
Regarding claim 1, Fig.10 of Freeman teaches a memory device, comprising:
a substrate (para.0025) comprising a memory array region 122 (para.0027) and a staircase region 124 (para.0027);
a stacked structure 100 (para.0025) located on the substrate (para.0025) in the memory array region 122 and the staircase region 124, wherein the stacked structure 320 comprises a plurality of conductive layers 112 (para.0025) and a plurality of insulating layers 114 (para.0025) stacked alternately;
a plurality of first through vias (see annotated Fig.10) located in the first 180 (para.0037) of the staircase region 124;
a plurality of second through vias (see annotated Fig.10) located in the second block 170 (para.0037) of the staircase region 124 and adjacent to the first through vias,
wherein a number of layers (see annotated Fig.10) of the stacked structure penetrated by the first through vias is smaller than a number of layers of the stacked structure penetrated by the second through vias (para.0041).
Freeman does not teach a separation wall 328 (para.0076) extending through the stacked structure to divide the stacked structure into a first block and a second block.
Fig.6 of SIM teaches, para.0041, wherein plurality of horizontal patterns 100a and 100b may be spaced apart from each other in the first direction D1 and the second direction D2 by a division region DV.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the division region of SIM in the teachings of Freeman because the division structure is configured to separate the source structures of adjacent memory structures from each other (SIM, abstract).
Regarding claim 2, Fig.6 of SIM further teaches the memory device according to claim 1, wherein the first through vias VS (para.0055) are landed on and electrically connected to an interconnection structure 100a (para.0055) on a substrate, and the second through vias PLG (para.0071) are landed on and electrically isolated from the interconnection structure 100a (para.0055).
Regarding claim 3, Freeman does not teach a plurality of contacts located in the second block of the staircase region and landed on the conductive layers.
Fig.6 of SIM teaches, para.0055, wherein vertical structures VS (wherein vertical structures are contacts) may be provided to penetrate the electrode structure ST in each mat region MTR (wherein mat region is staircase region) and wherein vertical structures VS may extend in t third direction D3 to horizontal patterns 100b (conductive layers).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the vertical structures VS of SIM, wherein the vertical structures extend to the horizontal patterns because the vertical structures VS including the semiconductor material may be used as channel regions of transistors constituting NAND cell strings (SIM, [para.0055]).
Regarding claim 13, Fig.10 of Freeman does not teach a separation wall extending through the staircase structure and dividing the staircase structure into a first block and a second block.
Fig.6 of SIM teaches a separation wall DIT (para.0067) extending through the staircase structure 150 (para.0065) and dividing the staircase structure 150 into a first block MTR (para.0051, wherein mat region is on horizontal patterns 100b) and a second block MTR (para.0051, wherein mat region is on horizontal patterns 100a).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the division region of SIM in the teachings of Freeman because the division structure is configured to separate the source structures of adjacent memory structures from each other (SIM, abstract).
Regarding claim 15, the combination of SIM and Freeman further teaches the memory device according to claim 13, wherein the recess region (see annotated Fig.10) is located in the first block 180 (para.0037), and the non-recess region (see annotated Fig.10) is located in the second block 170 (para.0037).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Freeman et al. (US20150214107A1) in view of SIM et al. (US20210036010A1) and in further view of Shimizu et al. (US9786680B2).
Regarding claim 4, the combination of Freeman and SIM appears not to explicitly disclose wherein a diameter of the first through vias is greater than a diameter of the second through vias. There is no evidence showing the criticality of the claimed difference in diameters of the first through vias and the second through vias.
The semiconductor art well recognizes that larger diameter of through-hole vias compared to smaller diameters controls parameters critical for device performance, including resistance (resistivity, length and cross sectional area) and mechanical viability (which includes mechanical strength as imparted by conductor thickness). Shimizu discloses, in annotated Fig.4 and col.6, lines 31-39, wherein the conductive pillars 41 that extend in the Z-direction can be formed by utilizing the stacked body 15n that is formed in the same process as the stacked body 15 for arranging the memory cell transistors along the Z-direction. Thereby, because the greater part of the current path extends in the Z-direction, the resistance element Er that has a high resistance value per unit surface area in the XY plane can be realized. As shown in annotated Fig.4, each of the second through vias has smaller diameter compared to each of the first through vias, and thus higher resistance. The diameter of the first and second through vias is therefore an art recognized result affecting parameter.
According to well established patent law precedents (see, for example, M.P.E.P. § 2144.05), therefore, it would have been obvious to determine (for example by routine experimentation) the optimum difference in diameters of the first through vias and the second through vias.
Annotated Figure 4
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Claims 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Freeman et al. (US20150214107A1) in view of Shimizu et al. (US9786680B2).
Regarding claim 10, Freeman further teaches the memory device according to claim 9, wherein the first through vias 120 (para.0041, wherein the conductive contacts 120 may be formed to extend from each conductive material 112 through the stair-step structure 100 to the substrate) extend through the first stepped portion (see annotated Fig.10); and second through vias 120 (para.0041, wherein the conductive contacts 120 may be formed to extend from each conductive material 112 through the stair-step structure 100 to the substrate) extend through the second stepped portion (see annotated Fig.10).
However, the combination of Freeman and SIM appears not to explicitly disclose wherein a diameter of the first through vias is greater than a diameter of the second through vias. There is no evidence showing the criticality of the claimed difference in diameters of the first through vias and the second through vias.
The semiconductor art well recognizes that larger diameter of through-hole vias compared to smaller diameters controls parameters critical for device performance, including resistance (resistivity, length and cross sectional area) and mechanical viability (which includes mechanical strength as imparted by conductor thickness). Shimizu discloses, in annotated Fig.4 and col.6, lines 31-39, wherein the conductive pillars 41 that extend in the Z-direction can be formed by utilizing the stacked body 15n that is formed in the same process as the stacked body 15 for arranging the memory cell transistors along the Z-direction. Thereby, because the greater part of the current path extends in the Z-direction, the resistance element Er that has a high resistance value per unit surface area in the XY plane can be realized. As shown in annotated Fig.4, each of the second through vias has smaller diameter compared to each of the first through vias, and thus higher resistance. The diameter of the first and second through vias is therefore an art recognized result affecting parameter.
According to well established patent law precedents (see, for example, M.P.E.P. § 2144.05), therefore, it would have been obvious to determine (for example by routine experimentation) the optimum difference in diameters of the first through vias and the second through vias.
Regarding claim 11, Freeman further teaches the memory device according to claim 10, further comprising: contacts 120 (para.0040) landed on the second stepped portion (see annotated Fig.10) and adjacent to the second through vias 120 (para.0041, wherein the conductive contacts 120 may be formed to extend from each conductive material 112 through the stair-step structure 100 to the substrate).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Freeman et al. (US20150214107A1) in view of SIM et al. (US20210036010A1) and in further view of Baek et al. (US20210151462A1).
Regarding claim 14, the combination of Freeman and SIM does not teach wherein the recess region and the non-recess region are located in the first block.
Baek teaches wherein the recess region SL (para.0081) and the non-recess region are located in the first block (see annotated Fig.3A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the slit regions of Baek in the teachings of Freeman and SIM because a slit region may be formed to be in contact with a pad region of a gate electrode and thus can lead to improved reliability of the device. (Baek, [para.0123]).
Claims 16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Freeman et al. (US20150214107A1) in view of Baek et al. (US20210151462A1).
Regarding claim 16, Freeman does not teach wherein the recess region comprises first recesses and second recesses staggered with each other, and respectively located at opposite sides of the memory array region of the substrate.
Fig.17A of Baek teaches wherein the recess region comprises first recesses MS1 (para.0069) and second recesses MS2 (para.0069) staggered with each other, and respectively located at opposite sides of the memory array region of the substrate.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the first and second separation regions MS1 and MS2 of Baek in the teachings of Freeman in order to enable the upper gate electrodes be at the same level. (Baek, [para.0069]).
Regarding claim 17, Freeman does not teach wherein adjacent recesses of two adjacent tiles are staggered with each other.
Fig. 17A of Baek teaches, para.0031, wherein adjacent recesses SS (para.0043) of two adjacent tiles are staggered with each other.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the upper separation regions of Baek in the teachings of Freeman in order to separate the gate electrodes 130 from each other in the Y direction (Baek, [para.0043]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINCENT KIPKEMOI RONO whose telephone number is (571)270-5977. The examiner can normally be reached Mon-Fri, 8am-5pm.
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VINCENT KIPKEMOI. RONO
Examiner
Art Unit 2891
/V.K.R./Examiner, Art Unit 2891
/TUCKER J WRIGHT/Primary Examiner, Art Unit 2891