Prosecution Insights
Last updated: April 19, 2026
Application No. 18/177,404

DOUBLE-SIDED REDISTRIBUTION LAYER (RDL) SUBSTRATE WITH DOUBLE-SIDED PILLARS FOR DEVICE INTEGRATION

Non-Final OA §103
Filed
Mar 02, 2023
Examiner
ZARNEKE, DAVID A
Art Unit
2891
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Qualcomm Incorporated
OA Round
3 (Non-Final)
71%
Grant Probability
Favorable
3-4
OA Rounds
2y 8m
To Grant
82%
With Interview

Examiner Intelligence

Grants 71% — above average
71%
Career Allow Rate
566 granted / 801 resolved
+2.7% vs TC avg
Moderate +11% lift
Without
With
+10.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
34 currently pending
Career history
835
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
59.3%
+19.3% vs TC avg
§102
24.5%
-15.5% vs TC avg
§112
7.2%
-32.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 801 resolved cases

Office Action

§103
DETAILED ACTION Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2/18/26 has been entered. Response to Arguments Applicant’s arguments, see the claim amendments filed 2/18/26, with respect to the rejection(s) of the claim(s) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made below. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Rejection over Liao et al., 10,283,443 Claim(s) 1, 5, and 31-34 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liao et al., 10,283,443, in view of O’Sullivan et al., US 2022/0310777. Regarding claim 1, Liao (see marked up figure 1 below) teaches a device, comprising: a redistribution layer (RDL) substrate 1; a metal-insulator-metal (MIM) capacitor C (column 2, lines 46-49) in the RDL substrate 1 proximate a second surface 2 of the RDL substrate 1; a first die 103 comprising a metallization layer 5 on a surface of the first die 103/D a first pair of conductive elements 109/109A coupled between the metallization layer 5 of the first die 103 and to the second surface 2 of the RDL substrate 1, opposite a first surface 3 of the RDL substrate 1, in which a conductive pillar 109 of the first pair of conductive pillars 109/109A is coupled between the metallization layer 105 on the surface of the die 103 and a plate 110 of the MIM capacitor C at the second surface 2 of the RDL substrate 1; and a laminate substrate (column 10, lines 13-18), comprising a metallization layer (column 10, lines 13-18 states electrically couple therefore a metallization layer mis present) on a first surface of the laminate substrate; and a second pair of conductive elements 118 coupled between the metallization layer on the first surface of the laminate substrate (column 10, lines 13-18) and the first surface 3 of the RDL substrate 1. PNG media_image1.png 488 800 media_image1.png Greyscale Laio fails to teach a first pair of pillars couple the first die to the second die and a second pair of conductive pillars couple the laminate substrate to the RDL substrate. O’Sullivan teaches a first pair of pillars 525 (paragraph 0056) couple the first die 520 and the second die to the RDL 210 (figure 5C); and a second pair of conductive pillars 595 (paragraph 0063) couple the laminate substrate 701 to the RDL substrate 210 (figure 7). It would have been obvious to one of ordinary skill in the art at the time of the invention to use the pillars of O’Sullivan in the invention of Laio because O’Sullivan (paragraphs 0056 & 0063) teaches the equivalence of the solder of Laio with pillars. The substitution of one known equivalent technique for another may be obvious even if the prior art does not expressly suggest the substitution (Ex parte Novak 16 USPQ 2d 2041 (BPAI 1989); In re Mostovych 144 USPQ 38 (CCPA 1964); In re Leshin 125 USPQ 416 (CCPA 1960); Graver Tank & Manufacturing Co. V. Linde Air Products Co. 85 USPQ 328 (USSC 1950). With respect to claim 5, Laio (figure 1) teaches the laminate substrate comprises a printed circuit board (column 10, lines 13-18) having a metallization layer to couple to the second pair of conductive pillars. In claim 8, though Liao fails to teach a three-dimensional 3D) [[3D]] inductor coupled to the MIM capacitor, it would have been obvious to one of ordinary skill in the art at the time of the invention to use a 3D inductor in the invention of Laio because it is conventionally known and used in the prior art. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07). Regarding claim 10, though Liao fails to teach the RDL substrate comprises a radio frequency (RF) filter, integrated in a radio frequency front-end (RFFE) module, it would have been obvious to one of ordinary skill in the art at the time of the invention to use this configuration in the invention of Liao because it is conventionally known and used in the prior art. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07). As to claim 31, Laio (figure 1) teaches in which the metallization layer 105 on the surface of the die 103 comprises a metal one (M1) metallization layer 105. In re claim 32, Laio (figure 1) teaches the conductive pillar 109 of the first pair of conductive pillars 109/109A is coupled between the M1 metallization layer 105 on the surface of the die 1 and an M1 metallization layer 110 on the second surface 2 of the RDL substrate 1. Concerning claim 33, Laio (figure 1) teaches a plate 110 of the MIM capacitor C comprises the M1 metallization layer 110 on the second surface 2 of the RDL substrate 1. Pertaining to claim 34, Laio (figure 1) teaches a conductive pillar 109 of the first pair of conductive pillars 109/109A is coupled between the M1 metallization layer 105 on the surface of the die 103 and the plate 110 of the MIM capacitor C. Rejections over Lee et al., US 8,335,084 Claim(s) 1, 5, 8, 10, 31-34 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al., US 8,335,084, in view of Liao et al., 10,283,443, and O’Sullivan et al., US 2022/0310777. With respect to claim 1, Lee (see marked up figure 3 below) teaches a device, comprising: a redistribution layer (RDL) substrate 16; a capacitor 22 in the RDL substrate proximate a second surface of the RDL substrate 16; a first die 25 comprising a metallization layer 27a on a surface of the first die 25 to couple to the second surface 2 of the RDL substrate 16, opposite a first surface 1 of the RDL substrate 16, through at least a first pair of conductive pillars 27, in which a conductive pillar 27 of the first pair of conductive pillars 27 is coupled between the metallization layer 27a on the surface of the die 25 and a plate 22 of the MIM capacitor 22 at the second surface 2 of the RDL substrate 16; and a laminate substrate 11 coupled to the first surface 1 of the RDL substrate 16 through at least a second pair 12 of conductive pillars 12. PNG media_image2.png 340 618 media_image2.png Greyscale Lee, which teaches a decoupling capacitor (column 3, line 66), fails to teach the capacitor is a metal-insulator-metal (MIM). Liao (column 2, lines 46-49) teaches a device, comprising a capacitor that is a MIM. It would have been obvious to one of ordinary skill in the art at the time of the invention to use a MIM capacitor of Liao in the invention of Lee because a MIM can be a decoupling capacitor. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07). Lee and Laio fail to teach a first pair of pillars couple the first die to the second die and a second pair of conductive pillars couple the laminate substrate to the RDL substrate. O’Sullivan teaches a first pair of pillars 525 (paragraph 0056) couple the first die 520 and the second die to the RDL 210 (figure 5C); and a second pair of conductive pillars 595 (paragraph 0063) couple the laminate substrate 701 to the RDL substrate 210 (figure 7). It would have been obvious to one of ordinary skill in the art at the time of the invention to use the pillars of O’Sullivan in the invention of Laio because O’Sullivan (paragraphs 0056 & 0063) teaches the equivalence of the solder of Laio with pillars. The substitution of one known equivalent technique for another may be obvious even if the prior art does not expressly suggest the substitution (Ex parte Novak 16 USPQ 2d 2041 (BPAI 1989); In re Mostovych 144 USPQ 38 (CCPA 1964); In re Leshin 125 USPQ 416 (CCPA 1960); Graver Tank & Manufacturing Co. V. Linde Air Products Co. 85 USPQ 328 (USSC 1950). As to claim 5, Lee (see marked up figure 3 above) teaches the laminate substrate 11 comprises a printed circuit board (column 3, lines 63-65) having a metallization layer 4 to couple to the second pair of conductive pillars 12. In re claim 8, Lee and Liao (as detailed in claim 1) teaches the passive component 22 comprises a metal-insulator-metal (MIM) capacitor and though Lee fails to teach further comprising a three-dimensional 3D inductor coupled to the MIM capacitor, it would have been obvious to one of ordinary skill in the art at the time of the invention to use an inductor in the invention of Lee because an inductor is conventionally known and used in combination with a MIM. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07). Concerning claim 10, in which the RDL substrate comprises a radio frequency (RF) filter, integrated in a radio frequency front-end (RFFE) module. Pertaining to claim 31, (Lee figure 3) teaches the metallization layer 27a on the surface of the die 25 comprises a metal one (M1) metallization layer. In claim 32, (Lee figure 3) teaches the conductive pillar 27 of the first pair of conductive pillars 27 is coupled between the M1 metallization layer 27a on the surface of the die 25 and an M1 metallization layer 22 on the second surface 2 of the RDL substrate 16. Regarding claim 33, (Lee figure 3) teaches a plate of the MIM capacitor 22 comprises the M1 metallization layer (top of 22) on the second surface 2 of the RDL substrate 16. With respect to claim 34, (Lee figure 3) teaches a conductive pillar 27 of the first pair of conductive pillars 27 is coupled between the M1 metallization layer (top of 22) on the surface of the die 25 and the plate of the MIM capacitor 22. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID A ZARNEKE whose telephone number is (571)272-1937. The examiner can normally be reached M-F. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matt Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DAVID A ZARNEKE/Primary Examiner, Art Unit 2891 2/27/26
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Prosecution Timeline

Mar 02, 2023
Application Filed
Aug 20, 2025
Examiner Interview (Telephonic)
Aug 20, 2025
Non-Final Rejection — §103
Oct 15, 2025
Examiner Interview Summary
Oct 15, 2025
Applicant Interview (Telephonic)
Nov 19, 2025
Response Filed
Dec 11, 2025
Final Rejection — §103
Jan 28, 2026
Examiner Interview Summary
Jan 28, 2026
Applicant Interview (Telephonic)
Feb 10, 2026
Response after Non-Final Action
Feb 18, 2026
Request for Continued Examination
Feb 26, 2026
Response after Non-Final Action
Feb 27, 2026
Non-Final Rejection — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
71%
Grant Probability
82%
With Interview (+10.8%)
2y 8m
Median Time to Grant
High
PTA Risk
Based on 801 resolved cases by this examiner. Grant probability derived from career allow rate.

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