DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/29/2026 has been entered.
Response to Amendment
The Amendment filed on 01/29/2026 has been entered. Claims 1, 5 and 6 remain pending in the application.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by disclosed prior art, Takada (Japanese Patent Application Publication Number, JP 202020538 A, attached machine translation), hereinafter referenced as Takada.
Regarding claim 1, Takada teaches a semiconductor device, comprising: a semiconductor chip (Fig.2, element #3, paragraph [0017], rows 1-4) comprising a first surface (Fig.2, bottom surface of element #3), a second surface (Fig.2, top surface of element #3), a first electrode electrically connected to the first surface (Fig.2, element #3A, paragraph [0019], rows 1-2), a second electrode electrically connected to the second surface (Fig.2, element #3B, paragraph [0019], rows 1-2), and a third electrode electrically connected to the second surface (paragraph [0019], rows 2-4); a first conductor (Fig.2, element #5, paragraph [0023], row 1) comprising first portion (Fig.2, formed by elements #5A and #5B) and a first intermediate portion (Fig.2, element #5C), the first portion being electrically connected to the second electrode (Fig.2, elements #5A and #3B are electrically connected through element #6B, paragraph [0032], rows 1-6), a direction from the semiconductor chip toward the first portion being along a first direction (Fig.2, first direction is Z direction), a direction from the first portion toward the first intermediate portion being along a second direction intersecting the first direction (Fig.2, second direction is X direction), the first portion being provided between the semiconductor chip and the first intermediate portion in the first direction (Fig.2, element #5A and #5B is provided between element #3 and element #5C in Z direction); a second conductor (Fig.2, element #4, paragraph [0023], row 1) comprising a third portion (Fig.2, portion of element #4C that is covered by element #6D), a second intermediate portion (Fig.2, element #4D), and a fourth portion (Fig.2, elements #4E), a direction from the third portion toward the fourth portion being along the second direction (Fig.2, a direction between the portion of element #4C that is covered by element #6D and element #4E is in X direction), a length of the first intermediate portion in the second direction being longer than a length of the third portion in the second direction (Fig.2, the length of element #5C in X direction is longer than the length of the portion of element #4C that is covered by element #6D, in X direction), and the second intermediate portion being provided between the third portion and the fourth portion in the second direction (Fig.2, element #4D is between the portion of element #4C that is covered by element #6D, and the fourth portion, element #4E, in X direction); a third conductor provided on a first surface side of the semiconductor chip (Fig.2, lead frame, element #1 is located on the bottom side of semiconductor chip, element #3); a conductive first connector provided between the first intermediate portion of the first conductor and the third portion of the second conductor (Fig.2, element #6D is provided between element #5C and the portion of element #4C covered by element #6D, paragraph [0037], rows 14-15); a conductive second connector provided between the second electrode of the semiconductor chip and the first portion of the first conductor (Fig.2, portion of element #6B located between elements #3B and #5A, paragraph [0032], rows 1-7); and a conductive third connector provided between the third conductor and the first electrode of the semiconductor chip (Fig.2, element #6A is provided between elements #1 and #3A, paragraph [0021], rows 1-4) wherein the first conductor (Fig.2, element #5) further includes a second portion (Fig.2, element #5D), the first intermediate portion is provided between the first portion and the second portion in the second direction(Fig.2, element #5C is provided between elements #5A and #5D in X direction), and a direction from the first portion toward the second portion is along the second direction (Fig.2, a direction between elements #5A and #5B and element #5D is in X direction), wherein the first connector is further provided between the second portion and the second intermediate portion (Fig.2, element #6D is provided between elements #5D and #4D), wherein the second portion extends in a fourth direction intersecting the first direction and the second direction (Fig.2, element #5D extends diagonally and intersect both X and Z directions), the second intermediate portion extends in the fourth direction (Fig.2, element #4D extends in the same direction as element #5D), and the first connector extends in the fourth direction (Fig.2, portion of element #6D located between element #4D and #5D extends in the same direction as element #5D), and wherein a direction from the third portion to the first intermediate portion is along the first direction (Fig.2, a direction from the portion of element #4C covered by element #6D to element #5C is along Z direction), and the third portion and the first intermediate portion are connected by the first connector (Fig.2, element #5C and the portion of element #4C that is coveted by element #6D, are connected by element #6D, paragraph [0037], rows 13-17), wherein the first connector is in contact with an entire upper surface of the third portion (Fig.2, element #6D is in contact with the entire top surface of the third portion, which is the portion of element #4C that is covered by element #6D), and wherein the second conductor is not in contact with the second connector and the second electrode (Fig.2, element #4 is not in contact with the second connector, which the portion of element #6B located between elements #3B and #5A and the second electrode, element #3B).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Takada, in view of Oga et al., (United States Patent Number, US 9,401,319 B2) hereinafter referenced as Oga.
Regarding claim 1, Takada teaches a semiconductor device, comprising: a semiconductor chip (Fig.2, element #3, paragraph [0017], rows 1-4) comprising a first surface (Fig.2, bottom surface of element #3), a second surface (Fig.2, top surface of element #3), a first electrode electrically connected to the first surface (Fig.2, element #3A, paragraph [0019], rows 1-2), a second electrode electrically connected to the second surface (Fig.2, element #3B, paragraph [0019], rows 1-2), and a third electrode electrically connected to the second surface (paragraph [0019], rows 2-4); a first conductor (Fig.2, element #5, paragraph [0023], row 1) comprising first portion (Fig.2, formed by elements #5A and #5B) and a first intermediate portion (Fig.2, element #5C), the first portion being electrically connected to the second electrode (Fig.2, elements #5A and #3B are electrically connected through element #6B, paragraph [0032], rows 1-6), a direction from the semiconductor chip toward the first portion being along a first direction (Fig.2, first direction is Z direction), a direction from the first portion toward the first intermediate portion being along a second direction intersecting the first direction (Fig.2, second direction is X direction), the first portion being provided between the semiconductor chip and the first intermediate portion in the first direction (Fig.2, element #5A and #5B is provided between element #3 and element #5C in Z direction); a second conductor (Fig.2, element #4, paragraph [0023], row 1) comprising a third portion (Fig.2, formed by elements #4A, #4B and #4C), a second intermediate portion (Fig.2, elements #4D), and a fourth portion (Fig.2, elements #4E), a direction from the third portion toward the fourth portion being along the second direction (Fig.2, a direction between the portion formed by element #4A, #4B, and #4C and element #4E is in X direction), a length of the first intermediate portion in the second direction being longer than a length of the third portion in the second direction (Fig.2, the length of element #5C in X direction is longer than the length of element #4C in X direction), and the second intermediate portion being provided between the third portion and the fourth portion in the second direction (Fig.2, element #4D is between the third portion, formed by elements #4A, #4B and #4C, and the fourth portion, element #4E, in X direction); a third conductor provided on a first surface side of the semiconductor chip (Fig.2, lead frame, element #1 is located on the bottom side of semiconductor chip, element #3); a conductive first connector provided between the first intermediate portion of the first conductor and the third portion of the second conductor (Fig.2, element #6D is provided between elements #5C and #4C, paragraph [0037], rows 14-15); a conductive second connector provided between the second electrode of the semiconductor chip and the first portion of the first conductor (Fig.2, portion of element #6B located between elements #3B and #5A, paragraph [0032], rows 1-7); and a conductive third connector provided between the third conductor and the first electrode of the semiconductor chip (Fig.2, element #6A is provided between elements #1 and #3A, paragraph [0021], rows 1-4) wherein the first conductor (Fig.2, element #5) further includes a second portion (Fig.2, element #5D), the first intermediate portion is provided between the first portion and the second portion in the second direction(Fig.2, element #5C is provided between elements #5A and #5D in X direction), and a direction from the first portion toward the second portion is along the second direction (Fig.2, a direction between elements #5A and #5B and element #5D is in X direction), wherein the first connector is further provided between the second portion and the second intermediate portion (Fig.2, element #6D is provided between elements #5D and #4D), wherein the second portion extends in a fourth direction intersecting the first direction and the second direction (Fig.2, element #5D extends diagonally and intersect both X and Z directions), the second intermediate portion extends in the fourth direction (Fig.2, element #4D extends in the same direction as element #5D), and the first connector extends in the fourth direction (Fig.2, portion of element #6D located between element #4D and #5D extends in the same direction as element #5D), and wherein a direction from the third portion to the first intermediate portion is along the first direction (Fig.2, a direction from element #4C to element #5C is along Z direction), and the third portion and the first intermediate portion are connected by the first connector (Fig.2, elements #5C and #4C are connected by element #6D, paragraph [0037], rows 13-17), wherein the second conductor is not in contact with the second connector and the second electrode (Fig.2, element #4 is not in contact with the second connector, which is the portion of element #6B located between elements #3B and #5A and the second electrode, element #3B). Tanaka teaches wherein the first connector is in contact to a portion of an upper surface of the third portion (Fig.2, element #6D is in contact with the right portion of the top surface of element #4C). Tanaka does not teach wherein, wherein the first connector is in contact with an entire upper surface of the third portion. Oga teaches a first connector (Fig.1, element #53) is in contact with an entire upper surface of a third portion (Fig.1, element #53 is in contact with an entire upper surface, element #62, of the top horizontal portion of second conductor, element #12). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Oga and disclose wherein the first connector is in contact with an entire upper surface of the third portion. Having the connector contact an entire upper surface of the second conductor increases the connection area between the two conductors, which provides increase mechanical stability.
Regarding claim 5, the combination of Takada and Oga teaches the semiconductor device of claim 1 as set forth in the obviousness rejection. Takada further teaches the semiconductor device according to claim 1, wherein the second surface is provided between the third portion and the first surface in the first direction (Fig.2, top surface of element #3 is provided between element #4A and the bottom surface of element #3).
Regarding claim 6, the combination of Takada and Oga teaches the semiconductor device of claims 1 and 5 as set forth in the obviousness rejection. Takada further teaches the semiconductor device according to claim 5, wherein a part of the third portion is provided between the semiconductor chip and the first intermediate portion (Fig.2, element #4A is provided between element #3 and element #5C).
Response to Arguments
Applicant’s arguments filed on 01/29/2026 have been fully considered but they
are not persuasive.
Regarding the 102 rejection of claim 1, as set forth in this office action, applicant’s arguments with respect to claim 1 have been considered but are not persuasive. The reference of Takada was applied differently in this office action as compared to the previous office action filed on 11/06/2025. The third portion of the second conductor was redefined as the portion of element #4C covered by the first connector, element #6D, and the second conductor was redefined as the portion of layer element #6B that is located between elements #3B and #5A. Therefore, the applicant arguments are moot.
Regarding the 103 rejection of claims 1, 5 and 6, as set forth in this office action, applicant’s arguments have been considered but are moot because the new grounds of rejection do not rely on any reference as applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/CRISTIAN A TIVARUS/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899