DETAILED ACTION
This action is responsive to the amendment received on 07/29/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I, Species A, and Species C in the reply filed on 07/30/2025 is acknowledged. Claim(s) 8, 14-16, 19, and 21-23 is/are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention or species, there being no allowable generic or linking claim.
Claim Interpretation
Claim 1 has been amended to recite “at least one of the adjustable first bias voltage and the second bias voltage is respectively independently adjustable after an integration period” and claim 9 has been amended to recite the limitation “the control circuitry is configured to adjust the first bias voltage, independent from the second bias voltage, such that the first bias voltage is different during a charge transfer period than during an integration period; and/or adjust the second bias voltage, independent from the first bias voltage, such that the second bias voltage is different during the charge transfer period than during the integration period”.
Apparatus claims cover what a device is, not what a device does (see MPEP 2114.II). The control circuitry in claim 9 is interpreted to describe the structure and the language relating to adjusting the various bias voltages at select time periods in claims 1 and 9 is interpreted as intended use. For the purposes of this examination, the manner of operating the device by changing the voltages in a particular manner will not differentiate the claims from the prior art if the prior art teaches all the structural limitations of the claim. Specifically, if the prior art discloses a device and/or control circuitry which is capable of adjusting the identified bias voltages at pre-defined time intervals, as described by the claim, it will be interpreted to read on the claim, even if the prior art does not disclose an identical procedure.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7, 9-13, 17, 18, 20, 29, 30, and 34-36 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0197754 A1; Jeon, Jongmim; 06/2023; (“Jeon”) in view of US 2024/0186357 A1; Takahashi et al.; 06/2024; (“Takahashi”) and US 2017/0229496 A1; Velichko et al.; 08/2017; (“Velichko”).
Regarding Claim 1. Jeon discloses A pixel cell (Figure 4, image sensor), comprising:
a front deep trench isolation (FDTI) structure (#150, Figure 4, first isolation region) disposed in a semiconductor material (#110, Figure 4, substrate which may be made of semiconductor material according to [0042] and #150 is disposed within) and extending a first depth from a frontside of the semiconductor material into the semiconductor material (Figure 4, #150 extends a first depth from front side #110F1 of #110 into #110), wherein the FDTI structure isolates a first region of the semiconductor material on a first side of the FDTI structure from a second region of the semiconductor material on a second side of the FDTI structure ([0050], “first isolation region 150 may physically and electrically isolate one photoelectric conversion device PD from an adjacent photoelectric conversion device PD”), wherein the FDTI structure includes a first conductive material (#154, Figure 4, conductive filling film) coupled to receive a first bias voltage ([0060], “the contact region 170 may provide a path for supplying a voltage to the first isolation region 150 by the power supply voltage”);
a back deep trench isolation (BDTI) structure (#160, Figure 4, second isolation region) disposed in the semiconductor material (Figure 4, #160 is disposed within #110) and extending a second depth from a backside of the semiconductor material into the semiconductor material (Figure 4, #160 extends a second depth, #160H, from back side #110F2 of #110 into #110), wherein the BDTI structure isolates the first region of the semiconductor material on a first side of the BDTI structure from the second region of the semiconductor material on a second side of the BDTI structure ([0053], “second isolation region 160 . . . may physically and electrically isolate one photoelectric conversion device PD from an adjacent photoelectric conversion device PD”), wherein the BDTI structure includes a second conductive material (#164, Figure 4, trap conductive film) coupled to receive a second bias voltage ([0055], “trap conductive film 164 including at least one electrically conductive material may be arranged to be electrically connected to the contact region 170”, i.e. #164 may receive a second bias voltage from the identified electrical connection), and
wherein the FDTI structure and BDTI structure are at least partially aligned in a depthwise direction of the semiconductor material (Figure 4, #150 and #160 are at least partially aligned in a z-direction of #110); and
a photodiode (#PD, Figure 4, photoelectric conversion device) disposed in the first region of the semiconductor material (Figure 4, #PDs are disposed in each region adjacent to a #150/#160) to accumulate image charge ([0026], “photoelectric conversion device PD may generate and accumulate photo-charge”), wherein the photodiode extends along the depthwise direction (Figure 4, #PDs extend along the z-direction) and is disposed proximate to at least a portion of the FDTI structure and a portion of the BDTI structure (Figure 4, #PDs are disposed proximate to a portion of both #150 and #160).
Jeon does not disclose that the first bias voltage is adjustable, and the second conductive material is coupled to receive an adjustable second bias voltage that is independent from the adjustable first bias voltage such that at least one of the adjustable first bias voltage and the adjustable second bias voltage is respectively independently adjustable after an integration period. As shown in Figure 4, and described in [0060] of Jeon, the second conductive material (#164) is coupled to the first conductive material (#154) through the contact region (#170) such that any applied voltage to one of the conductive materials will necessarily be the same as the applied voltage to the other conductor.
However, Takahashi teaches an imaging element pixel (#100, Figure 12) comprising a front deep trench isolation structure (#160, Figure 12, pixel isolation unit) extending into a semiconductor material (#125, Figure 12) and including a first conductive material (#109b, pixel isolation electrode), and a back deep trench isolation structure (#164, Figure 12, pixel isolation unit) extending into the semiconductor material (#125) and including a second conductive material (#109a, pixel isolation electrode), wherein the FDTI (#160) and the BDTI (#164) are aligned in a depthwise direction of the semiconductor material (#125) and isolate adjacent regions of the semiconductor material from one another as pixel isolation units,
wherein the first conductive material is coupled to receive a first adjustable bias voltage ([0213, a bias voltage may be applied to pixel isolation electrode #109b, the bias is interpreted as being adjustable based on the circuit diagram in Figure 2 and the timing diagram in Figure 6 showing that the bias #Vb1 applied to #109 may be changed at different time intervals), and
wherein the second conductive material is coupled to receive an adjustable second bias voltage that is different from the first adjustable bias voltage ([0213], “a different first bias voltage from that to the pixel isolation electrode 109a can be applied to the pixel isolation electrode 109b” and is further interpreted as adjustable based on the circuit and timing diagrams in Figures 2 and 6 respectively), and wherein at least one of the adjustable first bias voltage and the adjustable second bias voltage are respectively adjusted after an integration period (Figure 6, the bias voltages #Vb1 and #Vb2 may be adjusted at various time periods such as after an exposure/integration period T2-T4 such as during subsequent generation period T15 onwards).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider forming the appropriate electrical connections to allow different adjustable bias voltages to the first and second conductive materials, as was done by Takahashi, in the device of Jeon in order to allow for saturation charge amounts and dark currents of adjacent photodiodes to be adjusted/controlled on their respective opposing surfaces separately from one another (see [0214] of Takahashi).
Jeon in view of Takahashi do not disclose that the adjustable second bias voltage is independent from the adjustable first bias voltage such that at least one of the adjustable first bias voltage and the adjustable second bias voltage is respectively independently adjustable. Takahashi only explicitly discloses that the two bias voltages may be different from one another ([0213]) without describing how they are made to be different from one another.
However, Velichko teaches an imaging element pixel (#22, Figure 6) comprising a front deep trench isolation structure (right #114 in #102, Figure 6, trench structure in top layer of the pixel which functions as an isolation structure according to [0028]) extending into a semiconductor material (#102 of #100, Figure 6, n-implanted region of semiconductor substrate #100) and including a first conductive material (#136, Figure 6), and a back deep trench isolation structure (right #114 in #104, Figure 6, trench structure in bottom layer of the pixel which functions as an isolation structure according to [0028]) extending into the semiconductor material (#104 of #100, Figure 6) and including a second conductive material (#136, Figure 6), wherein the FDTI and the BDTI are aligned in a depthwise direction of the semiconductor material (Figure 6, #114s in #102 and #104 of #100 are aligned in a depthwise direction) and isolate adjacent regions of the semiconductor material from one another as pixel isolation units ([0028]),
wherein the first and second conductive materials is/are coupled to receive adjustable bias voltages (Figure 6, [0029], #130 may provide first and second bias voltages to the respective #136s through #124s, conductive layers, and #126s, contacts), and
wherein the adjustable second bias voltage is independent from the adjustable first bias voltage such that at least one of the adjustable first bias voltage and the adjustable second bias voltage is respectively independently adjustable. ([0032], “If desired, each contact may be coupled to an individual bias voltage supply line such that the bias voltage at each contact can be independently controlled”).
Since Jeon in view of Takahashi is silent regarding how the adjustable bias voltages are made to be different from one another, this would motivate one of ordinary skill to seek out teachings such as Velichko in order to practice the invention of Jeon in view of Takahashi. It would have been obvious to one of ordinary skill in the art, prior to the effective filing date of the claimed invention, to consider making the bias voltages of Jeon in view of Takahashi independently adjustable relative to one another as was done in Velichko if desired as taught by Velichko since doing so allows for improved control over the dark current and charge transfer during pixel operation to allow for improved performance as taught by Velichko in [0028].
Regarding Claim 2. Jeon in view of Takahashi and Velichko disclose The pixel cell of claim 1, further comprising a first electrically isolating material (Jeon, #152, Figure 4, insulating barrier) disposed between the first conductive material and the semiconductor material (Jeon, Figure 4, #152 is disposed between #154 and #110), and a second electrically isolating material (Jeon, #162, Figure 4, insulating liner) disposed between the second conductive material and the semiconductor material (Jeon, Figure 4, #162 is disposed between #164 and #110) (Takahashi, [0209]-[0210] describes that the pixel isolation structures are formed by first filling their corresponding grooves with insulating materials prior to the formation of their respective electrodes within those insulating materials) (Velichko, Figure 6 includes inversion layers #122, between the conductive materials and the semiconductor materials, which may be a dielectric according to [0025]).
Regarding Claim 3. Jeon in view of Takahashi and Velichko disclose The pixel cell of claim 1, wherein the FDTI structure is vertically aligned with the BDTI structure (Jeon, Figure 4, #150 and #160 are vertically aligned in a z-direction of #110; Takahashi, Figure 12, #160 is vertically aligned with #164; Velichko, Figure 6, #114s are vertically aligned between #102/#104 of #100).
Regarding Claim 4. Jeon in view of Takahashi and Velichko disclose The pixel cell of claim 1, wherein the adjustable first bias voltage operates to modulate a first electric potential of a first photodiode region proximate to the frontside of the semiconductor material (Jeon, Figure 4, [0050] and [0060], #150 including the potential applied to #154 functions to electrically isolate adjacent photodiodes such that it will necessarily modulate voltage potential of adjacent regions near #110F1), and the adjustable second bias voltage operates to modulate a second electric potential of a second photodiode region proximate to the backside of the semiconductor material (Jeon, Figure 4, [0053] and [0060], #160 including the potential applied to #164 functions to electrically isolate adjacent photodiodes such that it will necessarily modulate voltage potential of adjacent regions near #110F2) (Takahashi, [0214], the biases applied to the opposing isolation electrodes modifies the potential, saturation charge amounts, and dark currents of their respective sides of the semiconductor material) (Velichko, [0029], the biases applied to the opposing isolation electrodes modifies the potential of adjacent regions to manipulate the flow of electrons in/out of the adjacent regions during operation).
Regarding Claim 5. Jeon in view of Takahashi and Velichko disclose The pixel cell of claim 1.
Jeon in view of Takahashi and Velichko do not explicitly disclose that the first conductive material and the second conductive material are of different material.
However, Jeon does teach that the first conductive material and the second conductive material may be made from a list of generic known conductive materials and that the two structures are made during different fabrication steps (Figures 9 through 14, #154 and #164 are made at different points during fabrication such that they may be made of different material which may include doped polysilicon, titanium (Ti), tungsten (W), aluminum (Al), and indium tin oxide (ITO) for #164 and generically doped polysilicon or metal for #154). Furthermore, Velichko teaches in [0027] that “If desired, different portions of conductive layer 124 may be formed from different materials . . . any combination of conductive materials may be used to form conductive layer 124”.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider making the separate conductive structures of the front and back deep trench isolation structures in Jeon in view of Takahashi and Velichko of different materials as a mere substitution of equivalents known for the same purpose to achieve the predictable result of allowing an electrical bias to be applied to both structures (see MPEP 2144.06.II).
Regarding Claim 6. Jeon in view of Takahashi and Velichko disclose The pixel cell of claim 1 wherein the FDTI structure is in direct contact with the BDTI structure (Jeon, [0058], “the first isolation region 150 and the second isolation region 160 are in direct contact with each other”) (Velichko, Figure 6, opposing isolation trench structures are in direct contact with each other through layer #122 in each structure).
Regarding Claim 7. Jeon in view of Takahashi and Velichko disclose The pixel cell of claim 6, wherein the first conductive material and the second conductive material are electrically isolated (Jeon, [0058], “the first isolation region 150 and the second isolation region 160 . . . may not be electrically connected”, i.e. are electrically isolated by intervening insulating elements in Figure 4) (Takahashi, [0213], “a different first bias voltage from that to the pixel isolation electrode 109a can be applied to the pixel isolation electrode 109b”, i.e. the conductive electrodes are necessarily insulated from one another to allow the application of different bias voltages) (Velichko, Figure 6, opposing conductive materials are electrically isolated by layers #122 in each structure which may be a dielectric according to [0025]).
Regarding Claim 9. Jeon discloses An imaging system (#1000, Figure 19, electronic device including image sensor #1142 within camera modules, image sensor further detailed in Figure 21), comprising:
a pixel array (#1510, Figure 21, pixel array which may be #100, Figure 2-4, according to [0157]) having a plurality of pixel cells (#PX, Figure 2, unit pixel), wherein each of the plurality of pixel cells comprises:
a photodiode (#PD, Figures 3-4, photoelectric conversion device) disposed in an epitaxial layer (#110, Figure 4, substrate which may be epitaxially grown according to [0043]) in a first region of a semiconductor material (Figure 4, #PD are disposed in #110 which may be a semiconductor according to [0042]) to accumulate image charge ([0026], “photoelectric conversion device PD may generate and accumulate photo-charge”);
a front deep trench isolation (FDTI) structure (#150, Figure 4, first isolation region) disposed in the semiconductor material (#110, Figure 4, substrate which may be made of semiconductor material according to [0042] and #150 is disposed within) and extending a first depth from a frontside of the semiconductor material into the semiconductor material (Figure 4, #150 extends a first depth from front side #110F1 of #110 into #110), wherein the FDTI structure isolates the first region of the semiconductor material on a first side of the FDTI structure from a second region of the semiconductor material on a second side of the FDTI structure ([0050], “first isolation region 150 may physically and electrically isolate one photoelectric conversion device PD from an adjacent photoelectric conversion device PD”), wherein the FDTI structure includes a first conductive material (#154, Figure 4, conductive filling film) coupled to receive a first bias voltage ([0060], “the contact region 170 may provide a path for supplying a voltage to the first isolation region 150 by the power supply voltage”); and
a back deep trench isolation (BDTI) structure (#160, Figure 4, second isolation region) disposed in the semiconductor material (Figure 4, #160 is disposed within #110) and extending a second depth from a backside of the semiconductor material into the semiconductor material (Figure 4, #160 extends a second depth, #160H, from back side #110F2 of #110 into #110), wherein the BDTI structure isolates the first region of the semiconductor material on a first side of the BDTI structure from the second region of the semiconductor material on a second side of the BDTI structure ([0053], “second isolation region 160 . . . may physically and electrically isolate one photoelectric conversion device PD from an adjacent photoelectric conversion device PD”), wherein the BDTI structure includes a second conductive material (#164, Figure 4, trap conductive film) coupled to receive a second bias voltage ([0055], “trap conductive film 164 including at least one electrically conductive material may be arranged to be electrically connected to the contact region 170”, i.e. #164 may receive a second bias voltage from the identified electrical connection),
wherein the FDTI and BDTI structures are at least partially aligned in a direction from the frontside to the backside of the semiconductor material (Figure 4, #150 and #160 are at least partially aligned in a z-direction of #110), and
wherein each photodiode lies along the direction (Figure 4, #PDs extend along the z-direction) and proximate to at least a portion of the FDTI structure and a portion of the BDTI structure (Figure 4, #PDs are disposed proximate to a portion of both #150 and #160);
control circuitry (#1530, Figure 21, controller) coupled to the pixel array to control operation of the pixel array ([0159], “controller 1530 may control the row driver 1520 to allow the pixel array 1510 to absorb light to accumulate photo-charge . . .”); and
readout circuitry (#1212, Figure 19, sub-image processors) coupled to the pixel array to readout image data from the plurality of pixel cells (Figure 19, [0151], “corresponding sub-processor among the sub-image processors 1212a, 1212b, and 1212c of the image processing device 1210 may perform decoding, and may also perform image processing on the decoded image signal”, i.e. the sub-image processors read the image data from the camera modules containing the pixel arrays).
Jeon does not disclose that the second conductive material is coupled to receive a second bias voltage that is independent from the first bias voltage, and wherein the control circuitry is configured to
adjust the first bias voltage, independent from the second bias voltage, such that the first bias voltage is different during a charge transfer period than during an integration period; and/or adjust the second bias voltage, independent from the first bias voltage, such that the second bias voltage is different during the charge transfer period than during the integration period. As shown in Figure 4, and described in [0060] of Jeon, the second conductive material (#164) is coupled to the first conductive material (#154) through the contact region (#170) such that any applied voltage to one of the conductive materials will necessarily be the same as the applied voltage to the other conductive material.
However, Takahashi teaches a an imaging element pixel (#100, Figure 12) comprising a front deep trench isolation structure (#160, Figure 12, pixel isolation unit) extending into a semiconductor material (#125, Figure 12) and including a first conductive material (#109b, pixel isolation electrode), and a back deep trench isolation structure (#164, Figure 12, pixel isolation unit) extending into the semiconductor material (#125) and including a second conductive material (#109a, pixel isolation electrode), wherein the FDTI (#160) and the BDTI (#164) are aligned in a depthwise direction of the semiconductor material (#125) and isolate adjacent regions of the semiconductor material from one another as pixel isolation units, and
wherein the second conductive material is coupled to receive a second bias voltage that is different from the first bias voltage to the first conductive material ([0213], “a different first bias voltage from that to the pixel isolation electrode 109a can be applied to the pixel isolation electrode 109b”), and
wherein the control circuitry is configured to adjust the first bias voltage, the second bias voltage, or a combination thereof such that the first bias voltage, the second bias voltage, or the combination thereof is different during a charge transfer period than during an integration period (Figures 2 and 6, the bias voltages #Vb1 and #Vb2 may be adjusted by the control circuitry at various time periods such as after an exposure/integration period T2-T4 such as during subsequent charge transfer period T17 during which charges are transferred to charge holding units, see [0163], and voltages #Vb1 and #Vb2 are different from the first exposure/integration period).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider forming the appropriate electrical connections to allow different bias voltages to the first and second conductive materials, as was done by Takahashi, in the device of Jeon in order to allow for saturation charge amounts and dark currents of adjacent photodiodes to be adjusted/controlled on their respective opposing surfaces separately from one another (see [0214] of Takahashi).
Jeon in view of Takahashi do not disclose that the control circuitry is configured to
adjust the first bias voltage, independent from the second bias voltage and/or adjust the second bias voltage, independent from the first bias voltage. Takahashi only explicitly discloses that the two bias voltages may be different from one another ([0213]).
However, Velichko teaches an imaging element pixel (#22, Figure 6) comprising a front deep trench isolation structure (right #114 in #102, Figure 6, trench structure in top layer of the pixel which functions as an isolation structure according to [0028]) extending into a semiconductor material (#102 of #100, Figure 6, n-implanted region of semiconductor substrate #100) and including a first conductive material (#136, Figure 6), and a back deep trench isolation structure (right #114 in #104, Figure 6, trench structure in bottom layer of the pixel which functions as an isolation structure according to [0028]) extending into the semiconductor material (#104 of #100, Figure 6) and including a second conductive material (#136, Figure 6), wherein the FDTI and the BDTI are aligned in a depthwise direction of the semiconductor material (Figure 6, #114s in #102 and #104 of #100 are aligned in a depthwise direction) and isolate adjacent regions of the semiconductor material from one another as pixel isolation units ([0028]),
wherein the first and second conductive materials is/are coupled to receive adjustable bias voltages (Figure 6, [0029], #130 may provide first and second bias voltages to the respective #136s through #124s, conductive layers, and #126s, contacts), and
wherein the adjustable first bias voltage may be adjusted independent from the second bias voltage and/or adjust the adjustable second bias voltage independent from the first bias voltage ([0032], “If desired, each contact may be coupled to an individual bias voltage supply line such that the bias voltage at each contact can be independently controlled”).
Since Jeon in view of Takahashi is silent regarding how the adjustable bias voltages are made to be different from one another, this would motivate one of ordinary skill to seek out teachings such as Velichko in order to practice the invention of Jeon in view of Takahashi. It would have been obvious to one of ordinary skill in the art, prior to the effective filing date of the claimed invention, to consider making the bias voltages of Jeon in view of Takahashi independently adjustable relative to one another as was done in Velichko if desired as taught by Velichko since doing so allows for control over the dark current and charge transfer during pixel operation to allow for improved performance as taught by Velichko in [0028].
Regarding Claim 10. Jeon in view of Takahashi and Velichko disclose The imaging system of claim 9, wherein the second conductive material of the BDTI structure (Jeon, #164, Figure 4, trap conductive film) is connected to a contact pad (Jeon, Figure 4, rightmost #154, conductive filling film, which is not between pixels) through a metal interconnect in a first metal layer (Jeon, #170, Figure 4, contact region) proximate to the frontside of the semiconductor material (Jeon, Figure 4, front side #110F1 of #110; #164 is electrically connected to #170 as described above such that it is further connected to the rightmost #154, #170 is more proximate to the front side of the substrate #110F1 than #164 in that it is observed to extend to a greater depth towards #110F1, #170H) (Takahashi, [0214], Figure 12, #109a is physically connected to a contact pad (#143, contact plug) through a metal interconnect (#142) which is in a metal layer near the front (bottom) side of the semiconductor material #125) (Velichko, Figure 6, #136s in the layer #104 are at least physically connected to the contacts #126 near the frontside of #102 through a conductive layer #124 in #102).
Regarding Claim 11. Jeon in view of Takahashi and Velichko disclose The imaging system of claim 10, wherein the BDTI structure is one of a plurality of BDTI structures forming a BDTI structure grid (Jeon, Figure 3, BDTI grid structure; [0053], “the second isolation region 160 may be arranged in a lattice pattern (e.g., a mesh pattern or a grid pattern)”), and wherein at least one of the plurality of BDTI structures is connected to the contact pad (Jeon, [0055], “trap conductive film 164 including at least one electrically conductive material may be arranged to be electrically connected to the contact region 170” with #170 being electrically connected the rightmost #154 as described above) (Takahashi, Figure 12, #164 is part of a plurality of isolation, #164, electrode, #109, structures forming a grid, see Figures 11A-11D, wherein all of the #164s are physically connected to #143) (Velichko, Figure 6, [0027], #124s are in the formation of a mesh or grid structure all of which is physically connected to the #126s on the front).
Regarding Claim 12. Jeon in view of Takahashi and Velichko disclose The imaging system of claim 11, wherein the second conductive material of each of the plurality of BDTI structures are electrically connected together at the contact pad proximate to the backside of the semiconductor material (Jeon, Figures 3 and 4, #160s, being part of a continuous grid structure in the device are necessarily all electrically connected to one another and the contact pad #170 and rightmost #154, as described above, via the back side #110F2).
Regarding Claim 13. Jeon in view of Takahashi and Velichko disclose The imaging system of claim 10, further comprising an insulation material (Jeon, #152, Figure 4, insulating barrier of the rightmost #154) disposed between the contact pad and the semiconductor material (Jeon, Figure 4, #152 of the rightmost #154 is at least partially disposed between #154 and #110) (Takahashi, [0209]-[0210] describes that the pixel isolation structures are formed by first filling their corresponding grooves with insulating materials prior to the formation of their respective electrodes within those insulating materials which are between the electrodes and the semiconductor material) (Velichko, Figure 6 includes inversion layers #122, between the #126s and the semiconductor materials, which may be a dielectric according to [0025]).
Regarding Claim 17. Jeon in view of Takahashi and Velichko disclose The imaging system of claim 9, wherein the control circuitry operatively applies the first bias voltage (Jeon, [0060], “the contact region 170 may provide a path for supplying a voltage to the first isolation region 150 by the power supply voltage V.sub.DD”; power V.sub.DD is provided by the control circuitry according to [0153]) to the first conductive material of FDTI structure to modulate a first electric potential of a first photodiode region of the photodiode proximate to the frontside of the semiconductor material (Jeon, Figure 4, [0050] and [0060], #150 including the potential applied to #154 functions to electrically isolate adjacent photodiodes such that it will necessarily modulate voltage potential of adjacent regions near #110F1), and the second bias voltage to the second conductive material of BDTI structure to modulate a second electric potential of a second photodiode region of the photodiode proximate to the backside of the semiconductor material (Jeon, Figure 4, [0053] and [0060], #160 including the potential applied to #164 functions to electrically isolate adjacent photodiodes such that it will necessarily modulate voltage potential of adjacent regions near #110F2) (Takahashi, [0214], the biases applied to the opposing isolation electrodes modifies the potential, saturation charge amounts, and dark currents of their respective sides of the semiconductor material) (Velichko, [0029], the biases applied to the opposing isolation electrodes modifies the potential of adjacent regions to manipulate the flow of electrons in/out of the adjacent regions during operation).
Regarding Claim 18. Jeon in view of Takahashi and Velichko disclose The imaging system of claim 9, wherein the FDTI structure is vertically aligned (Jeon, Figure 4, #150 and #160 are vertically aligned in a z-direction of #110) and in direct contact with the BDTI structure (Jeon, [0058], “the first isolation region 150 and the second isolation region 160 are in direct contact with each other”; Velichko, Figure 6, #114s are vertically aligned between #102/#104 of #100 and opposing isolation trench structures are in direct contact with each other through layer #122 in each structure).
Regarding Claim 20. Jeon in view of Takahashi and Velichko disclose The imaging system of claim 9, wherein one or more of the first conductive material or the second conductive material comprises a doped polysilicon or a metal (Jeon, [0052], “conductive filling film 154 may include a conductive material, such as . . . doped polysilicon or metal”; [0055], “trap conductive film 164 may include at least one of, for example, doped polysilicon, titanium (Ti), tungsten (W), aluminum (Al), and indium tin oxide (ITO)”; Velichko, [0027], #124s may be polysilicon or metals including Al, W, and ITO).
Regarding Claim 29. Jeon in view of Takahashi and Velichko disclose The imaging system of claim 9, wherein:
the FDTI structure comprises a first pillar structure extending to the first depth from the frontside of the semiconductor material, wherein the first conductive material is positioned in a first core of the first pillar (Jeon, Figure 4, #150 comprises a pillar structure extending to a first depth into the #110 with #154 inside a core of the pillar; Takahashi, Figure 12, #160 comprises a pillar structure extending a first depth into #125 with #109b located inside a core of the pillar); and
the BDTI structure comprises a second pillar structure extending to the second depth from the backside of the semiconductor material, wherein the second conductive material is positioned in a second core of the second pillar (Jeon, Figure 4, #160 comprises a pillar structure extending to a second depth into the #110 with #164 inside a core of the pillar; Takahashi, Figure 12, #164 comprises a pillar structure extending a second depth into #125 with #109a located inside a core of the pillar) (Velichko, Figure 6, all of the #114s appear to comprise a pillar structure extending to a respective depth with their respective conductive materials #136 positioned in cores therein).
Regarding Claim 30. Jeon in view of Takahashi and Velichko disclose The imaging system of claim 9, wherein a first sidewall of the FDTI structure is aligned with a second sidewall of the BDTI structure along the direction from the frontside to the backside of the semiconductor material (Takahashi, Figure 12, the sidewalls of #160 and #164 are aligned with one another along a thickness direction of the semiconductor material #125; Velichko, Figure 6, the sidewalls of the #114s in layers #102 and #104 are vertically aligned with each other at the point where they make contact).
Regarding Claim 34. Jeon in view of Takahashi and Velichko disclose The imaging system of claim 9, wherein the control circuitry is configured to adjust the first bias voltage independently from the second bias voltage or the second bias voltage independently from the first bias voltage such that the second bias voltage is more negative than the first bias voltage during the charge transfer period (Velichko, [0032], “each contact may be coupled to an individual bias voltage supply line such that the bias voltage at each contact can be independently controlled” and [0029], the bias voltages may be adjusted by the control circuitry to be more negative/positive at various time periods to achieve values which are more/less negative than others as required during the periods described by Takahashi).
Regarding Claim 35. Jeon in view of Takahashi and Velichko disclose The imaging system of claim 9, wherein the control circuitry is configured to adjust the first bias voltage independently from the second bias voltage or the second bias voltage independently from the first bias voltage such that the first bias voltage is more negative than the second bias voltage during the charge transfer period (Velichko, [0032], “each contact may be coupled to an individual bias voltage supply line such that the bias voltage at each contact can be independently controlled” and [0029], the bias voltages may be adjusted by the control circuitry to be more negative/positive at various time periods to achieve values which are more/less negative than others as required during the periods described by Takahashi).
Regarding Claim 36. Jeon in view of Takahashi and Velichko disclose The pixel cell of claim 1, wherein the at least one of the adjustable first bias voltage and the adjustable second bias voltage are respectively independently adjusted after the integration period such that the second adjustable voltage is more negative than the first adjustable voltage during a charge transfer period (Velichko, [0032], “each contact may be coupled to an individual bias voltage supply line such that the bias voltage at each contact can be independently controlled” and [0029], the bias voltages may be adjusted by the control circuitry to be more negative/positive at various time periods to achieve values which are more/less negative than others as required during the periods described by Takahashi).
Response to Arguments/Amendments
Applicant’s amendments to independent claims 1 and 9 and corresponding arguments, see pages 10-15 of the remarks, filed 07/29/2026, with respect to the 35 U.S.C. 103 rejections of claims 1 and 9, and all 35 U.S.C. 103 rejections of their dependent claims, have been fully considered and are found persuasive. The originally cited prior art does not appear to disclose all of the limitations of amended claims 1 and 9. The original 35 U.S.C. 103 rejections of all claims are withdrawn. However, in view of the amendments, along with further search and consideration, new prior art has been identified which is interpreted to render the amended claims obvious. Claim(s) 1-7, 9-13, 17, 18, 20, 29, 30, and 34-36 stand(s) rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0197754 A1; Jeon, Jongmim; 06/2023; (“Jeon”) in view of US 2024/0186357 A1; Takahashi et al.; 06/2024; (“Takahashi”) and US 2017/0229496 A1; Velichko et al.; 08/2017; (“Velichko”).
Applicant correctly argues that the cited references do not explicitly disclose the amended limitations relating to bias voltages, which are independently adjustable from one another. Takahashi teaches that the bias voltages may be different from one another ([0213], “a different first bias voltage from that to the pixel isolation electrode 109a can be applied to the pixel isolation electrode 109b” and is further interpreted as adjustable based on the circuit and timing diagrams in Figures 2 and 6 respectively) which may encompass a loss in voltage from the input channels such that one of the voltages may be interpreted as independent (i.e. the set voltage) while the other voltage is dependent due to losses in the lines. Therefore, these voltages are not adequately described as independently adjustable because adjusting one may adjust the other in this case.
In view of applicant’s amendments, new art was identified (US 2017/0229496 A1; Velichko et al.; 08/2017; (“Velichko”)) which explicitly teaches conductive front and back deep trench isolation structures (see Figure 6 of Velichko) which receive bias voltages that may be independently adjusted from one another (Velichko, [0032], “If desired, each contact may be coupled to an individual bias voltage supply line such that the bias voltage at each contact can be independently controlled”) in order to allow for improved control over the dark current and charge transfer during pixel operation to allow for improved performance as taught by Velichko in [0028]. In view of this newly identified art, the amendments to independent claims 1 and 9 are interpreted as obvious. Claims 1 and 9 stand rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0197754 A1; Jeon, Jongmim; 06/2023; (“Jeon”) in view of US 2024/0186357 A1; Takahashi et al.; 06/2024; (“Takahashi”) and US 2017/0229496 A1; Velichko et al.; 08/2017; (“Velichko”).
Applicant’s remarks regarding dependent claims 2-7, 10-13, 17, 18, 20, 29, 30, and 34-36, see page 15 of the remarks, filed 07/29/2026, with respect to their allowability for their dependencies on independent claims 1 and 9 have been fully considered but are not found persuasive. As described above, claim(s) 1 and 9 stand rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0197754 A1; Jeon, Jongmim; 06/2023; (“Jeon”) in view of US 2024/0186357 A1; Takahashi et al.; 06/2024; (“Takahashi”) and US 2017/0229496 A1; Velichko et al.; 08/2017; (“Velichko”).
Applicant’s arguments regarding rejoinder of withdrawn claims 8, 14-16, 19, and 21-23, see page 16 of the remarks, filed 07/29/2026, with respect to their allowability for their dependencies on independent claims 1 and 9, or similar features to claims 1 and 9 in the case of claims 21-23, have been fully considered but are not found persuasive. As described above, claim(s) 1 and 9 stand rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0197754 A1; Jeon, Jongmim; 06/2023; (“Jeon”) in view of US 2024/0186357 A1; Takahashi et al.; 06/2024; (“Takahashi”) and US 2017/0229496 A1; Velichko et al.; 08/2017; (“Velichko”).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/TYLER J WIEGAND/Examiner, Art Unit 2812
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