Prosecution Insights
Last updated: April 19, 2026
Application No. 18/177,725

WIRING BOARD, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Non-Final OA §102
Filed
Mar 02, 2023
Examiner
PHAM, LONG
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Kioxia Corporation
OA Round
1 (Non-Final)
91%
Grant Probability
Favorable
1-2
OA Rounds
2y 6m
To Grant
97%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allow Rate
1493 granted / 1633 resolved
+23.4% vs TC avg
Moderate +6% lift
Without
With
+5.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
38 currently pending
Career history
1671
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
39.9%
-0.1% vs TC avg
§102
41.8%
+1.8% vs TC avg
§112
11.1%
-28.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1633 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of claims 1-12 and 13-15 in the reply filed on 8/5/25 is acknowledged. Further, the applicant failed to respond the species restriction of 8/5/25, for the restriction purpose, it is assumed that the elected claims are directed to species 1 (likely figures 1-9). Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, and 12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Niwa (US pub 20220005779). With respect to claim 1, Niwa teaches a wiring board, comprising (see figs. 1-14, particularly fig. 1 and associated text): a conductive layer 11 on a first surface (upper); and an insulating layer 14 covering a portion of the conductive layer, wherein the conductive layer includes: a first connection portion (part of 11 directly under 70, right) exposed from the insulating layer and having a first wettability to solder; a lead-out portion (part of 11 right of the first connection portion, right) connected to the first connection portion and exposed from the insulating layer and having a second wettability to solder; and a wiring portion (part of 11 directly under 14, right) connected to the first connection portion via the lead-out portion and covered with the insulating layer. With respect to claim 2, Niwa teaches an exposed surface of the first connection portion is coated with a gold layer. See para 0037. With respect to claim 3, Niwa teaches the lead-out portion is copper or a copper alloy. See para 0033. With respect to claim 6, Niwa teaches an upper surface of first connection portion facing away from the first surface is a plated gold layer. See fig. 1 and associated text and para 0037. With respect to claim 7, Niwa teaches the plated gold layer extends onto a side surface of the first connection layer but not onto the lead-out portion. See fig. 1 and associated text and para 0037. With respect to claim 8, Niwa teaches a copper pillar 21 extending in a direction away from the first surface, wherein the copper pillar is soldered to the first connection portion. See para 003. With respect to claim 9, Niwa teaches the solder does not extend onto the lead-out portion. See fig. 1 and associated text and para 0036. With respect to claim 10, Niwa teaches the copper pillar is connected to a semiconductor chip 20. See fig. 1 and associated text and para 0036. With respect to claim 11, Niwa teaches a height of the lead- out portion from the first surface and a height of the wiring portion from the first surface are substantially the same. See fig. 1 and associated text. With respect to claim 12, Niwa teaches the second wettability is lower than the first wettability (because of the presence the metal layer 70 over the first connection portion). See fig. 1 and associated text. Claim(s) 13, 14, and 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Niwa (US pub 20220005779). With respect to claim 13, Niwa teaches a semiconductor device, comprising (see figs. 1-14, particularly fig. 1 and associated text): a wiring board 10 with a conductive layer 11 on a first surface (upper) and an insulating layer 14 covering a portion of the conductive layer, the conductive layer including: a first connection portion (part of 11 directly under 70, right,) exposed from the insulating layer and having a first wettability to solder; a lead-out portion (part of 11 right of the first connection portion, right) connected to the first connection portion and exposed from the insulating layer and having a second wettability to solder; and a wiring portion (part of 11 directly under 14, right) connected to the first connection portion via the lead-out portion and covered with the insulating layer; and a first semiconductor element 20 with a first electrode 21 soldered to the first connection portion With respect to claim 14, Niwa teaches a second opening (left side where 70 occupies) is in the insulating layer, and the conductive layer further includes: a third connection portion (left 70) in the second opening, the third connection portion having an upper surface facing away from the first surface that is coated with a gold layer 70. See fig. 1 and associated text. With respect to claim 15, Niwa teaches a plurality of second semiconductor elements 30, 33 stacked on the first semiconductor element; and a wire connecting 90 right/left at least one of the second semiconductor elements and the third connection portion (11 of right and left edges). See fig. 1 and associated text. Examiner’s Cited References The cited references generally show the similar or related structure having a conductor having an exposed portion having overlying metal and an exposed portion and a portion under an insulating layer and a connector connected to the metal as presently claimed by applicant. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to LONG PHAM whose telephone number is (571)272-1714. The examiner can normally be reached Mon-Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. LONG . PHAM Examiner Art Unit 2823 /LONG PHAM/Primary Examiner, Art Unit 2897
Read full office action

Prosecution Timeline

Mar 02, 2023
Application Filed
Feb 05, 2026
Non-Final Rejection — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12604733
PACKAGE STRUCTURES WITH COLLAPSE CONTROL FEATURES
2y 5m to grant Granted Apr 14, 2026
Patent 12604754
PACKAGE STRUCTURES WITH NON-UNIFORM INTERCONNECT FEATURES
2y 5m to grant Granted Apr 14, 2026
Patent 12604766
SEMICONDUCTOR PACKAGE STRUCTURE
2y 5m to grant Granted Apr 14, 2026
Patent 12604739
Semiconductor Device and Method of Forming a 3-D Stacked Semiconductor Package Structure
2y 5m to grant Granted Apr 14, 2026
Patent 12599033
QUASI-MONOLITHIC INTEGRATED PACKAGING ARCHITECTURE WITH MID-DIE SERIALIZER/DESERIALIZER
2y 5m to grant Granted Apr 07, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

1-2
Expected OA Rounds
91%
Grant Probability
97%
With Interview (+5.6%)
2y 6m
Median Time to Grant
Low
PTA Risk
Based on 1633 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month