DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Species 1a and 2a, corresponding to claims 1, 2, and 4-11, in the reply filed on 11/20/25 is acknowledged.
Claim 3 will be rejoined as it is taught in elected figure 1, making the examined claims become 1-11.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3 is/are rejected under 35 U.S.C. 102a1 as being clearly anticipated by Chen et al., US 2020/0365593.
Regarding claim 1, Chen (see marked up figure 3 below) teaches a semiconductor storage device comprising:
a first layer 100A/101a including a first surface 1 and a second surface 2 located opposite to the first surface 1, the first layer 100A/101a including a first memory cell array 100A and a first wire layer 101a, the first memory cell array 100A being provided between the first surface 1 and the second surface 2 and including a plurality of first memory cells 100A, and the first wire layer 101a facing the first surface 1 and being electrically connected to the first memory cells 100A; and
a second layer 100B/101b including a third surface 3 and a fourth surface 4 located opposite to the third surface 3, the second layer 100B/101b including a second memory cell array 100B provided between the third surface 3 and the fourth surface 4 to be electrically connected to the first wire layer 101a and including a plurality of second memory cells 100B, wherein
the first layer 100A/101A and the second layer 100B/101B are joined together on the first surface 1 and the third surface 3.
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With respect to claim 2, Chen (see marked up figure 3 above) teaches the second layer 100B/101B further includes a second wire layer 101B facing the third surface 3 and electrically connected to the second memory cells 100B, and the first wire layer 101A and the second wire layer 101B are joined together on the first surface 1 and the third surface 3.
As to claim 3, Chen (see marked up figure 3 above) teaches the second layer 100B/101B further includes pads 7 facing the third surface 3 and electrically connected to the second memory cells 100B, and the first wire layer 100A/101A and the pads 7 are joined together on the first surface 1 and the third surface 3.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 4-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al., US 2020/0365593, as applied to claim 1 above, and further in view of Or-Bach et al., US 12,501,630.
In re claims 4-6, Chen (figure 1B & marked up figure 3 above) teaches the first layer 80 further includes a circuit 84 provided between the first memory cell array 84 and the second surface, and the first memory cells 80 and the second memory cells 80 are electrically connected (through TSVs of paragraph 0041)) to the circuit 84.
Chen fails to teach the circuit 84 is a CMOS (Complementary Metal Oxide Semiconductor) circuit.
Or-Bach (figure 2D & column 8, lines 35-52) teaches the memory circuit 212 is a CMOS (Complementary Metal Oxide Semiconductor) circuit, wherein a MOSFET is a type of CMOS.
It would have been obvious to one of ordinary skill in the art at the time of the invention to use CMOS/MOSFET circuit of Or-Bach in the invention of Chen because Or-Bach teaches CMOS is conventionally known and used in the art. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
In claims 7-9, Chen (see marked up figure 3 above) teaches a third layer 200 including a fifth surface 5 and a sixth surface 6 located opposite to the fifth surface 5 to be electrically connected (through TSV’s of paragraph 0041) to the first 100A and second memory cells 100B and the first wire layer 101a, wherein the first layer 100A/101A and the third layer 200 are joined together on the second surface 2 and the fifth surface 5.
Chen fails to teach the third layer including a CMOS circuit provided between the fifth surface and the sixth surface.
Or-Bach (figure 2D & column 8, lines 35-52) teaches the memory circuit 212 is a CMOS (Complementary Metal Oxide Semiconductor) circuit, wherein a MOSFET is a type of CMOS.
It would have been obvious to one of ordinary skill in the art at the time of the invention to use CMOS/MOSFET circuit of Or-Bach in the invention of Chen because Or-Bach teaches CMOS is conventionally known and used in the art. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
Regarding claim 10, Or-Bach teaches the first memory cell array includes a first layered member in which first insulating films (between conductors 1186) and first conductive films 1186 are layered alternately in a first direction, and a plurality of first columnar members 1184, each of which includes a first semiconductor portion and a charge trap film (column 39, line 43), the first semiconductor portion extending in the first layered member in the first direction and being electrically connected to the first wire layer 101a, and the charge trap film (column 39, line 43) being provided on an outer circumferential surface of the first semiconductor portion, and the second memory cell array includes a second layered member in which second insulating films (between conductors 1186) and second conductive films 1186 are layered alternately in the first direction, and a plurality of second columnar members 1184, each of which includes a second semiconductor portion and a charge trap film, the second semiconductor portion extending in the second layered member in the first direction and being electrically connected to the first wire layer 101a, and the charge trap film being provided on an outer circumferential surface of the second semiconductor portion.
With respect to claim 11, though Chen (see marked up figure 3 above) fails to teach the first wire layer is connected in common to the first semiconductor portions of the first columnar members, and is connected in common to the second semiconductor portions of the second columnar members, it would have been obvious to one of ordinary skill in the art at the time of the invention to use this configuration in the invention of Chen because it is conventionally known and used in the art. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The cited prior art teach inventions similar the claimed invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID A ZARNEKE whose telephone number is (571)272-1937. The examiner can normally be reached M-F.
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/DAVID A ZARNEKE/Primary Examiner, Art Unit 2891 1/13/26