Detailed Office Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
As of 6 January 2026, no Information Disclosure Statement has been filed.
Election/Restriction
Applicant's election with traverse of claims 1-9 in the reply filed on 4 November 2025 is acknowledged.
The restriction requirement for claims 1-15 and 21-25 is withdrawn.
Claims 1-15 and 21-25 are examined in this Office Action.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-15 and 21-25
Claims 1-15 and 21-25 are rejected under 35 U.S.C. 103 as being unpatentable over Enquist, Paul M. (2019/023719; “Enquist”) in view of Chen et al. (2020/0365544; “Chen”) and further in view of Lau, John H. (State-of-the-Art and Outlooks of Chiplets Heterogeneous Integration and Hybrid Bonding, IMAPS 2021 - 54th International Symposium on Microelectronics; “Lau”)
Regarding claim 1, Enquist discloses in figures 5, 7, and 12, and related figures and text, for example, Enquist – Selected Text, embodiments of bonds, and related processes, between substrates (for example, substrate 30 with substrate 32 and substrate 38 with substrate 39): “ Metal structures 4 are formed in dielectric 3. Metal structures 4 are located within dielectric 3 and can be a contact, pad, line, or other metal interconnect structure. Openings are formed in dielectric 3 over metal structures 4 followed by formation of barrier 2 and conductor 1.” Enquist, paragraph [0026].
Enquist - Figures 5, 7, and 12
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[0026] Referring now to the drawings, wherein like reference numerals designate like or corresponding parts throughout the several views, and more particularly to FIG. 1 showing a cross-section of a surface of a substrate 30 in a process for direct hybrid bonding according to the invention comprised of conductor 1, conductive barrier 2, dielectric 3, and metal structure 4. Metal structures 4 are formed in dielectric 3. Metal structures 4 are located within dielectric 3 and can be a contact, pad, line, or other metal interconnect structure. Openings are formed in dielectric 3 over metal structures 4 followed by formation of barrier 2 and conductor 1. The sizes and thicknesses of the conductor 1, conductive barrier 2 and metal structure 4 are not to scale but are drawn to illustrate the invention. While the openings and metal structures are shown to be the same size and shape, they can differ in size and shape depending upon design or need.
[0029] The upper surface of FIG. 1 is subjected to CMP to remove the portion of conductor 1 and conductive barrier 2 on top of dielectric 3. FIG. 2 illustrates the structure after CMP. The relative heights of conductor 1 and conductive barrier 2 relative to dielectric 3 can be controlled by the CMP portion of the damascene process.
[0030] There are a number of configurations of relative height of the conductor 1 and conductive barrier 2 to dielectric 3. The top surfaces of conductor 1 and barrier 2 can be below, even with, nominally even with or above the surface of dielectric 3. In general, direct hybrid bonding is possible with all configurations. However, a preferred configuration is where the relative heights of conductor 1 and conductive barrier 2 are below dielectric 3 by a distance t1. This configuration is conducive to formation of a void-free bond interface and is more manufacturable with regard to variation of the relative height across the bond surface. An example of variation of relative height across the bond surface of the conductive layers below dielectric 3 for a surface most suitable for direct hybrid bonding is one to ten nanometers below the dielectric 3, although smaller and larger variations are also possible. This recess is typically referred to as dishing. The resulting surface is referred to as a hybrid bond surface without a conductive barrier 2.
[0032] As shown in FIG. 3, a layer of conductive barrier metal 6 is formed over the structure on surface 31 shown in FIG. 2. Barrier 6 can be the same or a different material than conductive barrier 2. Formation of barrier 6 on top of the conductor 1 after increased dishing can be formed in a number of ways, for example by a damascene process including deposition of the conductive barrier over the entire surface followed by CMP to remove the conductive barrier from the higher dielectric surface without removing a significant amount or all of the conductive barrier material of layer 6 from within the recess. The barrier formation may also be formed with a selective process, for example electro-less nickel electroplating. The resulting structure has conductive barrier 7 in each of the openings 5 on top of conductor 1 and conductive barrier 2. This resulting dishing is preferably compatible with that required for a direct hybrid bond, i,e, the surface of conductive barrier 7 is less than 20 nm, and preferably 1-10 nm, below the surface of dielectric 3. The cross-section of the resulting surface shown schematically in FIG. 4 is referred to as a hybrid bond surface with a conductive barrier 7.
[0034] Each hybrid bond surface of substrate 30 can contain devices and/or integrated circuits (not shown) such that these devices and/or integrated circuits can be connected to each other after completion of the hybrid bond. The devices and circuits can contain metal structures 4 or can be connected to metal structures 4 through further unillustrated interconnect structures.
[0035] Two hybrid bond surfaces of substrates 30 and 32 each having with a conductive barrier 7 with cross-section schematic such as shown in FIG. 4 can now be direct hybrid bonded to each other as shown in the cross-sections of FIGS. 5 and 6 to form direct hybrid bond 12. Substrates 30 and 32 are aligned (FIG. 5) and placed into direct contact such that the dielectric layers 3 in substrates 30 and 32 contact each other (FIG. 6). The alignment and contacting can be performed at room temperature in either room ambient or under vacuum. Although the figures schematically show a gap between the barriers 7 of substrates 30 and 32, there may be partial or significant contact between barriers 7 following the alignment and contacting. While a one-to-one connection arrangement is shown in FIG. 6, other arrangements are possible such as plural metal structures in one substrate are bonded to a single metal structure in another substrate.
[0036] The dielectric surfaces of substrates 30 and 32 are preferably prepare… Briefly, the surfaces may be etched, polished, activated and/or terminated with a desired bonding species to promote and enhance chemical bonding between dielectric 3 on substrates 30 and 32. Smooth surfaces of dielectric 3 with a roughness of 0.1 to 3 nm rms are produced which are activated and/or terminated through wet or dry processes.
[0037] As the substrate surfaces contact at room temperature, the dielectric 3 of the substrate surfaces began to form a bond at a contact point or points, and the attractive bonding force between the wafers increases as the chemically bonded area increases. This contact can include barriers 7 or not include barriers 7. If the contact includes barriers 7, the pressure generated by the chemical substrate-to-substrate bonding in dielectric 3 results in a force by which contacting areas of the barriers 7 are strongly joined, and the chemical bonding between the dielectric 3 in substrates 30 and 32 produces electrical connection between metal pads on the two different wafers. The internal pressure of barriers 7 against each other resulting from the bond between the dielectric 3 of substrates 30 and 32 may not be adequate to achieve an electrical connection with a preferably low resistance due to, for example, a native oxide or other contamination, for example, hydrocarbons. An improved bond or preferably lower resistance electrical connection may be achieved by removing the native oxide on barrier 7. …
[0041] FIG. 9 illustrates the upper portion of two substrates 34 and 35 with hybrid bond surfaces. Hybrid bond surfaces with a conductive barrier can comprise via components 8 that are connected to underlying trace components (not shown) or trace components 9 that are connected to underlying via components (not shown). After bonding, there is typically some amount of misalignment between respective hybrid bond surfaces with a conductive barrier. This misalignment can result in contact of conductive barrier 7 on a first hybrid bond surface with a dielectric surface 6 on a second hybrid bond surface and contact of a dielectric surface 6 on a first hybrid bond surface with a conductive barrier 7 on a second hybrid bond surface as shown by 10 in FIG. 9. This misalignment can also result in contact of conductive barrier 7 on one hybrid bond surface with dielectric surface 6 on another surface and the contact of an entire surface of conductive barrier 7 from one surface with a portion of a surface of a conductive barrier 7 on the other hybrid bond surface as shown by 11 in FIG. 9.
[0042] Notwithstanding this misalignment, the surface of dielectric 3 on either first or second hybrid bond surface is in contact with either conductive barrier 7 on the other hybrid bond surface and conductive barrier 7 on either first or second hybrid bond surface is in contact with either conductive barrier 7 or the surface of dielectric 3 on the other hybrid bond surface according to the present invention. The conductive barrier 7 on top of conductor 1 thus prevents contact between conductor 2 and dielectric 3 notwithstanding misalignment. This feature of the subject invention can improve reliability of the direct hybrid bond, for example when Cu is used as conductor 1 with Cu single or dual damascene direct hybrid bond surfaces built in a Cu BEOL for applications where there is a concern, for example, of Cu diffusion into dielectric 3 if Cu was in direct contact with dielectric 3. The feature may also facilitate the formation of an electrical connection across the bond interface for some structures, for example where conductor 1 is a W plug single damascene direct hybrid bond surfaces built in an Al BEOL when making electrical connections between conductor 1 on opposing surfaces is more challenging than making electrical connections between conductive barriers 7 on top of conductors 1 on opposing surfaces.
[0048] Two hybrid bond surfaces of substrates 38 and 39 with a conductive barrier 16 formed as shown in the cross-section schematic of FIG. 11 can now be direct hybrid bonded to each other as shown in the cross-section of FIG. 12 to form direct hybrid bond with conductive barrier 16 without an underlying conductive barrier. Each hybrid bond surface is a surface of a substrate and each substrate can contain devices and/or integrated circuits such that these devices and/or integrated circuits can be connected to each other after completion of the hybrid bond. Hybrid bond surfaces with a conductive barrier can comprise via components that are connected to underlying trace components (not shown) or trace components 19 that are connected to underlying via components (not shown).
[0049] After bonding, there is typically some amount of misalignment between respective hybrid bond surfaces with a conductive barrier. This misalignment can result in contact of conductive barrier 16 on a first hybrid bond surface with a dielectric surface 17 on a second hybrid bond surface in substrate 36 and contact of a dielectric surface 17 on a first hybrid bond surface with a conductive barrier 16 on a second hybrid bond surface as shown by 20 in FIG. 12. This misalignment can also result in contact of conductive barrier 16 on one hybrid bond surface with dielectric surface 17 on another surface and the contact of an surface of conductive barrier 16 from one surface with a portion of a surface of a conductive barrier 16 on the other hybrid bond surface as shown by 21 in FIG. 12.
[0050] Notwithstanding this misalignment, dielectric surface 17 on either first or second hybrid bond surface is in contact with either conductive barrier 16 on the other hybrid bond surface and conductive barrier 16 on either first or second hybrid bond surface is in contact with either conductive barrier 16 or dielectric surface 17 on the other hybrid bond surface according to the present invention. This feature can facilitate the formation of an electrical connection across the bond interface for some structures, for example where conductor 13 is an Al routing surface built in an Al BEOL, when making electrical connections between conductor 13 on opposing surfaces is more challenging than making electrical connections between conductive barriers 16 on top of conductors 13 on opposing surfaces.
Further regarding claim 1, while Enquist discloses bond embodiments comprising horizontal and vertical electrical connections (circuits) at substrate (chip) interfaces, for example, wiring connecting transistors; Enquist, figures 5, 7, and 12, and related figures and text, for example, Enquist – Selected Text; Enquist does not explicitly disclose that the bond embodiments participate in semiconductor configurations having vertically disposed interposers
However, Chen discloses in Figure 1A, and related figures and text, embodiments of encapsulated semiconductor packages 10A comprising dies 100 and 200 (the dies having different widths) disposed on vertically stacked levels, the chips supported, separated, and/or connected by redistribution layers, for example, 101R, and interposer layers (for example, as defined by through via pillars 103; and the dies comprising photonic integrated circuits, for example, die 200 in figure 2A . Chen, figures 1A and 2A, and related figures and text, for example, Chen – Selected Text.
Chen - Figures 1A and 2A
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Chen – Selected Text
[0020] Referring to FIG. 1, the semiconductor package structure 10A may include a first semiconductor die 100 and a second semiconductor die 200. The first semiconductor die 100 has an active surface 100A and a passive surface 100P opposite to the active surface 100A. The active surface 100A of the first semiconductor die 100 is the surface formed with the active devices (not shown) of the first semiconductor die 100. Conductive bumps 1001 are in proximity to, adjacent to, or embedded in and exposed at active surface 100A, serving as a medium for signal input/output, wherein each conductive bumps 1001 electrically and mechanically connects a bonding pad (not shown) of the first semiconductor die 100 and the redistribution layer (RDL) 102R. Thereby, the signals from the first semiconductor die 100 can be transmitted to the second semiconductor die 200 via the conductive bumps 1001 and the RDL 102R.
[0021] As illustrated in FIG. 1A, a plurality of conductive elements 103 are disposed beside, or leveled with, the first semiconductor die 100. By leveling with the first semiconductor die 100, a bottom of each of the conductive elements may be coplanar with a bottom of the first semiconductor die 100. In some embodiments, a bottom of each of the conductive elements and a bottom of the first semiconductor die 100 are both disposed on a top surface of the RDL 101R. In some embodiments, molding compound 105 encapsulates the first semiconductor die 100 and the conductive elements 103. In some embodiments, the conductive element 103 can be a copper pillar or a through package via (TPV). RDL 102R over the first semiconductor die 100 is disposed to be closer to the active surface 100A than the passive surface 100P. RDL 101R under the first semiconductor die 100 is disposed to be closer to the passive surface 100P than the active surface 100A. Substrate 300 is disposed to be closer to the passive surface 100P than the active surface 100A. Conductive traces 1021R and 1022R in the RDL 102R can be configured in a fan-out structure with respect to the first semiconductor die 100, in which a projection area of the conductive trances 1021R and 1022R in the RDL 102R may be greater than a projection area of the first semiconductor die 100. Conductive traces 1011R in the RDL 101R may be connected to the passive surface 100P of the first semiconductor die 100. Conductive traces 1012R in the RDL 101R may be connected to the bottom of the conductive elements 103 encapsulated in the molding compound 105.
[0038] Referring to FIG. 2A, FIG. 2A illustrates a cross-sectional view of a semiconductor package structure 20A according to some embodiments of the present disclosure. The second semiconductor die 200 in the semiconductor package structure 20A can be a PIC having a waveguide layer 203, for example, disposed in proximity to the active surface 200A. The semiconductor package structure 20A further includes an optical fiber 207 optically coupled to the waveguide layer 203 through, for example, a pair of reflectors 209A, 209B, and a coupler 205. As shown in FIG. 2A, the optical fiber 207 is disposed over a passive surface 200P of the second semiconductor die 200. Reflector 209A can be machined in the body of the second semiconductor die 200 by a MEMS procedure so as to alter the optical path from a horizontal direction to a vertical direction, for example. The optical path is then altered again at the reflector 209B machined in the coupler 205 from a vertical direction to a horizontal direction, and subsequently propagating into the optical fiber 207. To reduce optical loss, boundaries between the passive surface 200P of the second semiconductor die 200 and the coupler 205 may father include a layer of anti-reflective coating (ARC) (not shown).
Consequently, in light of Chen’s disclosure of semiconductor packages; Chen, paragraph [0020] (disclosing …“a first semiconductor die 100 and a second semiconductor die 200. The first semiconductor die 100 has an active surface 100A and a passive surface 100P opposite to the active surface 100A. The active surface 100A of the first semiconductor die 100 is the surface formed with the active devices (not shown) of the first semiconductor die 100. Conductive bumps 1001 are in proximity to, adjacent to, or embedded in and exposed at active surface 100A, serving as a medium for signal input/output, wherein each conductive bumps 1001 electrically and mechanically connects a bonding pad (not shown) of the first semiconductor die 100 and the redistribution layer (RDL) 102R. Thereby, the signals from the first semiconductor die 100 can be transmitted to the second semiconductor die 200 via the conductive bumps 1001 and the RDL 102R.”); it would have been obvious to one of ordinary skill in the art to modify Enquist’s embodiments to disclose: a first interposer comprising: a first substrate; first optical components over the first substrate; a first dielectric layer over the first optical components; and first conductive connectors embedded in the first dielectric layer; a photonic package bonded to a first side of the first interposer, wherein a first bond between the first interposer and the photonic package comprises a dielectric-to-dielectric bond between a second dielectric layer on the photonic package and the first dielectric layer, and a second bond between the first interposer and the photonic package comprises a metal-to-metal bond between a second conductive connector on the photonic package and a first one of the first conductive connectors; and a first die bonded to the first side of the first interposer; Enquist, figures 5, 7, and 12, and related figures and text, for example, Enquist – Selected Text; Chen, figure 1A, and related figures and text, for example, Chen – Selected Text; because the resulting configuration would facilitate designing, fabricating, and deploying heterogeneous 2D and 3D packages. Lau, figures 7, 18, and 19, and related figures and text, for example, Lau, Integration Packaging (“Chiplet design and heterogeneous integration packaging contrast with SoC. As pointed out in … that heterogeneous integration uses packaging technology to integrate dissimilar chips, photonic devices, or components (either side by side, stacked, or both) with different sizes and functions, and from different fabless design houses, foundries, wafer sizes, feature sizes and companies into a system or subsystem on a common package substrate. These chips can be any kind of devices and don’t have to be chiplets. On the other hand, for chiplets, they have to use the heterogeneous integration to package them …A chiplet is a functional integrated circuit block that is often made of reusable IP (intellectual property) blocks.”).
Lau - Figures 7, 18, and 19
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Regarding independent claims 10 and 21, it would have been obvious to one of ordinary skill in the art to modify Enquist in view of Chen and further in view of Lau, as applied in the rejection of claim 1, to disclose:
10. A package comprising: a first interposer; a first package component over and bonded to a first side of the first interposer, the first package component comprising first optical components; and a first semiconductor die over and bonded to the first side of the first interposer, the first interposer comprising second optical components that are optically connected to the first optical components, wherein the second optical components extend under both the first package component and the first semiconductor die. Enquist, figures 5, 7, and 12, and related figures and text, for example, Enquist – Selected Text; Chen, figure 1A, and related figures and text, for example, Chen – Selected Text; Lau, figures 7, 18, and 19, and related figures and text.
21. A semiconductor package comprising: a photonic package bonded to a first side of a first interposer, wherein a first bond between the first interposer and the photonic package comprises a dielectric-to-dielectric bond between a first dielectric layer on the photonic package and a second dielectric layer of the first interposer, and a second bond between the first interposer and the photonic package comprises a metal-to-metal bond between a first conductive connector on the photonic package and a second conductive connector of the first interposer, wherein the second conductive connector is embedded in the second dielectric layer; a first die bonded to the first side of the first interposer; and a second interposer coupled to a second side of the first interposer, wherein a width of the second interposer is greater than a width of the first interposer. Enquist, figures 5, 7, and 12, and related figures and text, for example, Enquist – Selected Text; Chen, figure 1A, and related figures and text, for example, Chen – Selected Text; Lau, figures 7, 18, and 19, and related figures and text.
because the resulting configurations would facilitate designing, fabricating, and deploying heterogeneous 2D and 3D packages. Lau, figures 7, 18, and 19, and related figures and text, for example, Lau, Integration Packaging.
Regarding claims 2-9, as dependent upon claim 1, claims 11-15, as dependent upon claim 10, and claims 22-25, as dependent upon claim 1, it would have been obvious to one of ordinary skill in the art to modify Enquist in view of Chen and further in view of Lau’s embodiments, as applied in the rejection of claims 1, 10, and 21, to disclose:
2. The semiconductor package of claim 1, wherein the photonic package comprises: a first redistribution structure; an electronic die bonded to the first redistribution structure; and a laser diode adjacent to the electronic die and bonded to the first redistribution structure. Enquist, figures 5, 7, and 12, and related figures and text, for example, Enquist – Selected Text; Chen, figure 1A, and related figures and text, for example, Chen – Selected Text; Lau, figures 7, 18, and 19, and related figures and text.
3. The semiconductor package of claim 1, wherein a third bond between the first interposer and the first die comprises a dielectric-to-dielectric bond between a third dielectric layer on the first die and the first dielectric layer, and a fourth bond between the first interposer and the first die comprises a metal-to-metal bond between a third conductive connector on the first die and a second one of the first conductive connectors. Enquist, figures 5, 7, and 12, and related figures and text, for example, Enquist – Selected Text; Chen, figure 1A, and related figures and text, for example, Chen – Selected Text; Lau, figures 7, 18, and 19, and related figures and text.
4. The semiconductor package of claim 1, wherein the first optical components of the first interposer extend under both the first die and the photonic package. Enquist, figures 5, 7, and 12, and related figures and text, for example, Enquist – Selected Text; Chen, figure 1A, and related figures and text, for example, Chen – Selected Text; Lau, figures 7, 18, and 19, and related figures and text.
5. The semiconductor package of claim 1, wherein the first optical components of the first interposer are optically coupled to second optical components of the photonic package. Enquist, figures 5, 7, and 12, and related figures and text, for example, Enquist – Selected Text; Chen, figure 1A, and related figures and text, for example, Chen – Selected Text; Lau, figures 7, 18, and 19, and related figures and text.
6. The semiconductor package of claim 1, further comprising: a second interposer coupled to a second side of the first interposer using fourth conductive connectors on the second interposer and fifth conductive connectors on the first interposer, wherein the first side of the first interposer and the second side of the first interposer are opposite sides. Enquist, figures 5, 7, and 12, and related figures and text, for example, Enquist – Selected Text; Chen, figure 1A, and related figures and text, for example, Chen – Selected Text; Lau, figures 7, 18, and 19, and related figures and text.
7. The semiconductor package of claim 6, further comprising: a memory device coupled to a first side of the second interposer using sixth conductive connectors on the memory device and seventh conductive connectors on the second interposer, the memory device and the first interposer being coupled to a same side of the second interposer. Enquist, figures 5, 7, and 12, and related figures and text, for example, Enquist – Selected Text; Chen, figure 1A, and related figures and text, for example, Chen – Selected Text; Lau, figures 7, 18, and 19, and related figures and text.
8. The semiconductor package of claim 7, further comprising: a package substrate coupled to a second side of the second interposer using eighth conductive connectors. Enquist, figures 5, 7, and 12, and related figures and text, for example, Enquist – Selected Text; Chen, figure 1A, and related figures and text, for example, Chen – Selected Text; Lau, figures 7, 18, and 19, and related figures and text.
9. The semiconductor package of claim 7, further comprising: a second die in the second interposer, wherein the first die, the photonic package, and the memory device are electrically interconnected through metal lines built inside the second die. Enquist, figures 5, 7, and 12, and related figures and text, for example, Enquist – Selected Text; Chen, figure 1A, and related figures and text, for example, Chen – Selected Text; Lau, figures 7, 18, and 19, and related figures and text. Enquist, figures 5, 7, and 12, and related figures and text, for example, Enquist – Selected Text; Chen, figure 1A, and related figures and text, for example, Chen – Selected Text; Lau, figures 7, 18, and 19, and related figures and text.
11. The package of claim 10, further comprising: a third package component coupled to a second side of the first interposer; and a fourth package component coupled to the third package component, wherein the third package component comprises a second interposer, and the fourth package component comprises a memory device. Enquist, figures 5, 7, and 12, and related figures and text, for example, Enquist – Selected Text; Chen, figure 1A, and related figures and text, for example, Chen – Selected Text; Lau, figures 7, 18, and 19, and related figures and text.
12. The package of claim 11, wherein the second interposer comprises one or more dies that are used to electrically connect the first package component, the first semiconductor die, and the fourth package component through metal lines inside the one or more dies. Enquist, figures 5, 7, and 12, and related figures and text, for example, Enquist – Selected Text; Chen, figure 1A, and related figures and text, for example, Chen – Selected Text; Lau, figures 7, 18, and 19, and related figures and text.
13. The package of claim 10, wherein a first bond between the first interposer and the first package component comprises a dielectric-to-dielectric bond between a first dielectric layer on the first interposer and a second dielectric layer on the first package component, and a second bond between the first interposer and the first package component comprises a metal-to- metal bond between a first conductive connector on the first package component and a corresponding one of second conductive connectors on the first interposer. Enquist, figures 5, 7, and 12, and related figures and text, for example, Enquist – Selected Text; Chen, figure 1A, and related figures and text, for example, Chen – Selected Text; Lau, figures 7, 18, and 19, and related figures and text.
14. The package of claim 13, wherein a third bond between the first interposer and the first semiconductor die comprises a dielectric-to-dielectric bond between the first dielectric layer on the first interposer and a third dielectric layer on the first semiconductor die, and a fourth bond between the first interposer and the first semiconductor die comprises a metal-to-metal bond between a third conductive connector on the first semiconductor die and a corresponding one of the second conductive connectors on the first interposer. Enquist, figures 5, 7, and 12, and related figures and text, for example, Enquist – Selected Text; Chen, figure 1A, and related figures and text, for example, Chen – Selected Text; Lau, figures 7, 18, and 19, and related figures and text.
15. The package of claim 10, wherein the first optical components comprise silicon, and the second optical components comprise silicon nitride. Enquist, figures 5, 7, and 12, and related figures and text, for example, Enquist – Selected Text; Chen, figure 1A, and related figures and text, for example, Chen – Selected Text; Lau, figures 7, 18, and 19, and related figures and text. Here, the examiner notes that it would have been obvious to one of ordinary skill in the art to deploy silicon and/or silicon nitride optical configurations because silicon and/or silicon nitride optical configurations are well-known, well-understood, and oft-used optical configurations.
22. The semiconductor package of claim 21, wherein the photonic package comprises: first optical components; a first redistribution structure over the first optical components; an electronic die bonded to the first redistribution structure; and a laser diode adjacent to the electronic die and bonded to the first redistribution structure. Enquist, figures 5, 7, and 12, and related figures and text, for example, Enquist – Selected Text; Chen, figure 1A, and related figures and text, for example, Chen – Selected Text; Lau, figures 7, 18, and 19, and related figures and text.
23. The semiconductor package of claim 21, further comprising a memory device coupled to a first side of the second interposer using third conductive connectors. Enquist, figures 5, 7, and 12, and related figures and text, for example, Enquist – Selected Text; Chen, figure 1A, and related figures and text, for example, Chen – Selected Text; Lau, figures 7, 18, and 19, and related figures and text. The examiner notes that Lau discloses HBMs (High Bandwidth Memory).
24. The semiconductor package of claim 23, further comprising: a package substrate coupled to a second side of the second interposer using fourth conductive connectors, wherein the first side of the second interposer and the second side of the second interposer are opposite sides of the second interposer. Enquist, figures 5, 7, and 12, and related figures and text, for example, Enquist – Selected Text; Chen, figure 1A, and related figures and text, for example, Chen – Selected Text; Lau, figures 7, 18, and 19, and related figures and text.
25. The semiconductor package of claim 24, wherein a width of the package substrate is greater than a width of the second interposer. Enquist, figures 5, 7, and 12, and related figures and text, for example, Enquist – Selected Text; Chen, figure 1A, and related figures and text, for example, Chen – Selected Text; Lau, figures 7, 18, and 19, and related figures and text.
because the resulting configurations would facilitate designing, fabricating, and deploying heterogeneous 2D and 3D packages. Lau, figures 7, 18, and 19, and related figures and text, for example, Lau, Integration Packaging.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER RADKOWSKI whose telephone number is (571)270-1613. The examiner can normally be reached on M-Th 9-5. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thomas Hollweg, can be reached on (571) 270-1739. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/PETER RADKOWSKI/Primary Examiner, Art Unit 2874