DETAILED ACTION 1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. 2. This Non-Final office action is in response to application 18/178,375, application filed on 03/03/2023. Claims 1-20 are currently pending in this application. Claim Rejections - 35 USC § 102 3 . The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 4 . Claim(s) 1 -6, 10-14 and 18-19 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Migatz et al. (US PG Pub No. 2006/0190899) . 5. With respect to independent claim 1, Migat z teaches : A method of generating a clock tree for a circuit ( generating clock distribution network for an integrated circuit, Abstract; clock tree generation, para 2; clock tree leaf elements, para 17; clock tree construction, para 16 ) , the method comprising: clustering synchronous logic cells of the circuit according to their interactive timing behavior ( clustering of clocked [synchronous] elements, para 16; grouping clock tree leaf elements into a cluster, para 19, 38, 77; see timing behavior as timing constraints on slack and congestion for sub-regions/cluster, Abstract; cluster based on cost function including timing analysis, Abstract; clock tree clustering which may alter timing requirements, cause timing violations, etc , para 6 ; clock tree leaf element includes synchronized elements to a clock signal, para 2 ) ; placing resulting clusters of the synchronous logic cells in the circuit in cells of diamond-shaped patches ( see Fig 5, showing placement of latches/FF’s [synchronous logic cells] placed in diamond shape patches, as shown in Fig 5, para 68-70 ) ; and generating the clock tree as traces from centers of the patches to the cells ( see clock tree, tracing from center of diamond shape to cells see binary search/trace, Fig 3, para 63 ) . 6. With respect to independent claim 10, Migat z teaches : cluster synchronous logic cells of a circuit according to their interactive timing behavior ( clustering of clocked [synchronous] elements, para 16; grouping clock tree leaf elements into a cluster, para 19, 38, 77; see timing behavior as timing constraints on slack and congestion for sub-regions/cluster, Abstract; cluster based on cost function including timing analysis, Abstract; clock tree clustering which may alter timing requirements, cause timing violations, etc , para 6; clock tree leaf element includes synchronized elements to a clock signal, para 2 ) ; place resulting clusters of the synchronous logic cells in the circuit in cells of diamond-shaped patches ( see Fig 5, showing placement of latches/FF’s [synchronous logic cells] placed in diamond shape patches, as shown in Fig 5, para 68-70 ) , the placement of the resulting clusters made with higher priority over placement of asynchronous logic cells of the circuit ( determining regions of clocked elements, and then other nets/cells which may be combinational/asynchronous, para 15-16; placement of clock tree leaf elements [synchronous elements] are first determined, para 37; see clocked sequential elements are placed, then combinational network clouds consisting of logic gates can be placed, but which are devoid of storage synchronous elements, para 66 ) ; and generate a right-angled clock tree between the cells and between the patches ( see right-angle clock network/tree structure connecting diamond shaped regions/patches to rest of layout network/tree structure as shown in Fig 3 and Fig 9, para 15-18, 75-78 ) . 7. With respect to independent claim 18, Migat z teaches : cluster synchronous logic cells of the circuit ( clustering of clocked [synchronous] elements, para 16; grouping clock tree leaf elements into a cluster, para 19, 38, 77; see timing behavior as timing constraints on slack and congestion for sub-regions/cluster, Abstract; cluster based on cost function including timing analysis, Abstract; clock tree clustering which may alter timing requirements, cause timing violations, etc , para 6; clock tree leaf element includes synchronized elements to a clock signal, para 2 ) ; place resulting clusters of the synchronous logic cells in the circuit in cells of diamond-shaped patches ( see Fig 5, showing placement of latches/FF’s [synchronous logic cells] placed in diamond shape patches, as shown in Fig 5, para 68-70 ) , the cells generated by repeatedly sub-dividing the diamond shaped patches into smaller cells ( see diamond-shaped regions/patches in Fig 7, then see sub-regions inside diamond-shaped regions/patches as shown in Fig 7, para 72-75 ) ; and generate portions of a clock tree within the patches ( see clock network/tree structure connecting diamond shaped regions/patches to rest of layout network/tree structure as shown in Fig 3 and Fig 9, para 15-18, 75-78 ; see clock/tree structure as shown in Fig 3 in one diamond-shaped region/patch, para 63-65 ) . 8 . With respect to claim 2 , Migat z teaches : The method of claim 1, further comprising: placing the resulting clusters of synchronous logic cells in the circuit with higher priority than placement of asynchronous logic cells ( determining regions of clocked elements, and then other nets/cells which may be combinational/asynchronous, para 15-16; placement of clock tree leaf elements [synchronous elements] are first determined, para 37; see clocked sequential elements are placed, then combinational network clouds consisting of logic gates can be placed, but which are devoid of storage synchronous elements, para 66 ) . 9 . With respect to claim 3 , Migat z teaches : The method of claim 1, wherein the interactive timing behavior comprises an intensity and criticality of signaling between the synchronous logic cells ( see critical connection with clock tree leaf element, para 46; see critical path of slack cells, para 5; timing critical failures, slack requirements, para 3-5, 41-45 ) . 1 0 . With respect to claim 4 , Migat z teaches : The method of claim 1, wherein larger ones of the resulting clusters of the synchronous logic cells are placed before smaller ones of the resulting clusters of the synchronous logic cells ( assigned nearby cells to larger clusters, para 72, para 72; driving larger elements, para 3; see large synchronous elements clustered, then combinational cloud cells placed, Fig 7; determining regions of clocked elements, and then other nets/cells which may be combinational/asynchronous, para 15-16; placement of clock tree leaf elements [synchronous elements] are first determined, para 37; see clocked sequential elements are placed, then combinational network clouds consisting of logic gates can be placed, but which are devoid of storage synchronous elements, para 66 ) . 1 1 . With respect to claim 5 , Migat z teaches : The method of claim 1, wherein a proximity of placement of the resulting clusters to one another is determined by one or both of an intensity of interaction between the resulting clusters and a criticality of timing between the resulting clusters ( see interactions between wiring and connection of nets in diamond shaped regions, para 61; see critical connection with clock tree leaf element, para 46; see critical path of slack cells, para 5; timing critical failures, slack requirements, para 3-5, 41-45 ) . 1 2 . With respect to claim 6 , Migat z teaches : The method of claim 1, wherein the resulting clusters of the synchronous logic cells are placed in cells resulting from repeatedly sub-dividing the diamond-shaped patches ( see clusters and diamond regions shown in Fig 7, where multiple diamond regions are shown, including sub-regions, para 12-15 ) . 1 3 . With respect to claim 1 1 , Migat z teaches : The computer-readable storage medium of claim 10, wherein the instructions when executed by the computer further cause the computer to: place larger ones of the resulting clusters in the circuit before smaller ones of the resulting clusters ( assigned nearby cells to larger clusters, para 72, para 72; driving larger elements, para 3; see large synchronous elements clustered, then combinational cloud cells placed, Fig 7; determining regions of clocked elements, and then other nets/cells which may be combinational/asynchronous, para 15-16; placement of clock tree leaf elements [synchronous elements] are first determined, para 37; see clocked sequential elements are placed, then combinational network clouds consisting of logic gates can be placed, but which are devoid of storage synchronous elements, para 66 ) . 1 4 . With respect to claim 1 2 , Migat z teaches : The computer-readable storage medium of claim 10, wherein the instructions when executed by the computer further cause the computer to: determine a proximity of placement of the resulting clusters to one another based at least on an intensity of interaction between the resulting clusters ( see interactions between wiring and connection of nets in diamond shaped regions, para 61; see critical connection with clock tree leaf element, para 46; see critical path of slack cells, para 5; timing critical failures, slack requirements, para 3-5, 41-45 ) . 1 5 . With respect to claim 1 3 , Migat z teaches : The computer-readable storage medium of claim 10, wherein the instructions when executed by the computer further cause the computer to: determine a proximity of placement of the resulting clusters to one another based at least on a criticality of timing between the resulting clusters ( see interactions between wiring and connection of nets in diamond shaped regions, para 61; see critical connection with clock tree leaf element, para 46; see critical path of slack cells, para 5; timing critical failures, slack requirements, para 3-5, 41-45 ) . 1 6 . With respect to claim 1 4 , Migat z teaches : The computer-readable storage medium of claim 10, wherein the instructions when executed by the computer further cause the computer to: place the resulting clusters in cells resulting from repeatedly sub-dividing the diamond-shaped patches ( see clusters and diamond regions shown in Fig 7, where multiple diamond regions are shown, including sub-regions, para 12-15 ) . 17 . With respect to claim 19, Migat z teaches : The computing apparatus of claim 18, wherein the instructions further configure the apparatus to: place the resulting clusters of synchronous logic cells in the circuit with higher priority than placement of asynchronous logic cells ( determining regions of clocked elements, and then other nets/cells which may be combinational/asynchronous, para 15-16; placement of clock tree leaf elements [synchronous elements] are first determined, para 37; see clocked sequential elements are placed, then combinational network clouds consisting of logic gates can be placed, but which are devoid of storage synchronous elements, para 66 ) . Claim Rejections - 35 USC § 103 18. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness . 19. Claim(s ) 7-9, 15-17 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Migatz et al. (US PG Pub No. 2006/0190899) in view of Ebeling et al. (US Patent No. 9, 922,157 ) . 20 . With respect to claim 7, while Migatz appears to be silent regarding the limitation(s) below, Ebeling teaches : The method of claim 6, the cells resulting from repeatedly sub-dividing cells of the diamond shaped patches into four smaller cells ( see division of cells into 4 partitions, or 9 partitions, or 16 partitions, Fig 5-9 ) . It would have been obvious to one of ordinary skill in the art before the time of the invention to have incorporated Ebeling’s division of timing tree structure into multiple areas/regions for at least the following reason(s): as described in Ebeling, dividing the clock tree into subtrees allows for skew/slack partition allocation and performance can be improved by a combination of clock tree construction and placement in an IC design, which also improves the IC design of Migatz by improving performance of the IC chip design . 21 . With respect to claim 8, while Migatz appears to be silent regarding the limitation(s) below, Ebeling teaches : The method of claim 6, the cells resulting from repeatedly sub-dividing cells of the diamond shaped patches into nine smaller cells ( see division of cells into 4 partitions, or 9 partitions, or 16 partitions, Fig 5-9 ) . (For motivation to combine references, please see rejection of claim 7). 2 2 . With respect to claim 9, while Migatz appears to be silent regarding the limitation(s) below, Ebeling teaches : The method of claim 6, the cells resulting from repeatedly sub-dividing cells of the diamond shaped patches into sixteen smaller cells ( see division of cells into 4 partitions, or 9 partitions, or 16 partitions, Fig 5-9 ) . (For motivation to combine references, please see rejection of claim 7). 2 3 . With respect to claim 15, while Migatz appears to be silent regarding the limitation(s) below, Ebeling teaches : The computer-readable storage medium of claim 14, wherein the instructions when executed by the computer further cause the computer to: repeatedly sub-divide the cells of the diamond shaped patches into four smaller cells ( see division of cells into 4 partitions, or 9 partitions, or 16 partitions, Fig 5-9 ) . (For motivation to combine references, please see rejection of claim 7). 2 4 . With respect to claim 16, while Migatz appears to be silent regarding the limitation(s) below, Ebeling teaches : The computer-readable storage medium of claim 14, wherein the instructions when executed by the computer further cause the computer to: repeatedly sub-divide the cells of the diamond shaped patches into nine smaller cells ( see division of cells into 4 partitions, or 9 partitions, or 16 partitions, Fig 5-9 ) . (For motivation to combine references, please see rejection of claim 7). 2 5 . With respect to claim 17, while Migatz appears to be silent regarding the limitation(s) below, Ebeling teaches : The computer-readable storage medium of claim 14, wherein the instructions when executed by the computer further cause the computer to: repeatedly sub-divide the cells of the diamond shaped patches into sixteen smaller cells ( see division of cells into 4 partitions, or 9 partitions, or 16 partitions, Fig 5-9 ) . (For motivation to combine references, please see rejection of claim 7). 2 6 . With respect to claim 20, while Migatz appears to be silent regarding the limitation(s) below, Ebeling teaches : The computing apparatus of claim 18, the cells generated by repeatedly sub-dividing cells of the diamond shaped patches into four, nine, or sixteen smaller cells ( see division of cells into 4 partitions, or 9 partitions, or 16 partitions, Fig 5-9 ) . (For motivation to combine references, please see rejection of claim 7). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUCHIN PARIHAR whose telephone number is (703)756-1970. The examiner can normally be reached on M-F 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. 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If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SUCHIN PARIHAR/ Primary Examiner, Art Unit 2851