Prosecution Insights
Last updated: October 24, 2026
Application No. 18/178,389

SELECTOR DEVICE AND SEMICONDUCTOR DEVICE INCLUDING THE SAME

Non-Final OA §102§103
Filed
Mar 03, 2023
Priority
Jun 17, 2022 — RE 10-2022-0074256
Examiner
PAYEN, MARVIN
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
SK hynix Inc.
OA Round
1 (Non-Final)
77%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
80%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
367 granted / 474 resolved
+9.4% vs TC avg
Minimal +3% lift
Without
With
+2.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
5 currently pending
Career history
483
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
61.0%
+21.0% vs TC avg
§102
29.6%
-10.4% vs TC avg
§112
5.8%
-34.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 474 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Species I (claims 1-7) in the reply filed on 11 May 2026 is acknowledged. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1 and 5-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Horii et al. (2021/00167285, from hereinafter “Horii”). Re Claim 1. Horii discloses in Figs. 2 and 20, a selector device, comprising: a first electrode layer (194); a second electrode layer (224) disposed to be spaced apart from the first electrode layer; a selector layer (214) disposed between the first electrode layer and the second electrode layer and configured to perform a threshold switching operation by trapping conductive carriers or releasing trapped conductive carriers depending on an external voltage applied to the selector layer; and one or more barrier layers (204, 206) disposed between the first electrode layer and the selector layer, or between the selector layer and the second electrode layer, or both between the first electrode layer and the selector layer and between the selector layer and the second electrode layer, wherein at least one of the one or more barrier layers includes a two-dimensional layered material [0015]-[0038] and [0076]-[0078]. Re Claim 5. Horii discloses in [0025]-[0034], wherein the two-dimensional layered material includes graphene-based two-dimensional layered materials, two-dimensional chalcogenide-based materials, two-dimensional oxide-based materials, phosphorous-based two-dimensional layered materials, or a combination of two or more of the graphene-based two-dimensional layered materials, the two-dimensional chalcogenide-based materials, the two-dimensional oxide-based materials, or the phosphorous-based two-dimensional layered materials. Re Claim 6. Horii discloses in [0025]-[0034], wherein the two-dimensional layered materials include graphene, black phosphorus (BP), transition metal dichalcogenide (TMD), hexagonal boron nitride (hBN) or a combination of two or more of the graphene, the BP, the TMD, or the hBN. Re Claim 7. Horii discloses, wherein at least one of the one or more barrier layers includes a monolayer or a multilayer structure of the two-dimensional layered material. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over Horii, and further in view of Lee (2017/0256589). Re Claim 2. Horii fails to disclose, wherein the selector layer includes an oxide. However, Lee discloses: wherein a selector layer (layer 220 of selection element 32) includes an oxide [0035]-[0041]. Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. Re Claim 3. Lee discloses, wherein the oxide includes silicon oxide, metal oxide, or a combination of the silicon oxide and the metal oxide [0035]-[0041]. Re Claim 4. Lee discloses, wherein the selector layer includes a dopant doped into the oxide [0035]-[0041]. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARVIN PAYEN whose telephone number is (571)270-7435. The examiner can normally be reached on Monday-Thursday, Fridays off. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached on (571)272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MARVIN PAYEN/Primary Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Mar 03, 2023
Application Filed
Oct 07, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12761875
SEMICONDUCTOR DEVICE
4y 2m to grant Granted Oct 13, 2026
Patent 12765029
FIELD EFFECT TRANSISTOR WITH NARROWED SPACER AND METHOD
3y 1m to grant Granted Oct 13, 2026
Patent 12765364
TIER RECESS METHOD
2y 6m to grant Granted Oct 13, 2026
Patent 12745574
SEMICONDUCTOR DEVICE, MEMORY CELL AND METHOD OF FORMING THE SAME
2y 7m to grant Granted Sep 22, 2026
Patent 12740341
MEMORY CELL, SEMICONDUCTOR DEVICE INCLUDING MEMORY CELL, AND MANUFACTURING METHOD THEREOF
3y 2m to grant Granted Sep 15, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
77%
Grant Probability
80%
With Interview (+2.8%)
2y 10m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 474 resolved cases by this examiner. Grant probability derived from career allowance rate.

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