DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of claims
Claims 1-6, 8-11, 15, 16, 27-29 are pending. Claim 29 is newly added. Claims 7 and 29 are withdrawn. Claims 12-14, 17-26 canceled.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on April 15, 2026 has been entered.
Election/Restrictions
Regarding new claim 29. Claim 29 recites the limitation “wherein the gate electrode, the gate dielectric layer, the vertical pattern, the air gap, and the back gate electrode are sequentially stacked in a horizontal direction perpendicular to the vertical direction”.
Nonelected species VII FIG. 7 requires [0123] Each of the dielectric structures 432 may include only an air gap 432_AG.
Applicant’s elected species I, FIG. 3 requires a spacer (FIG. 3, item 132_S1) between the air gap (FIG. 3, item 132_AG) and the vertical pattern (FIG. 3, item 140).
Applicant’s claim 29 is directed to non-elected species VII, FIG. 7.
Claim 29 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species VII, FIG. 7, there being no allowable generic or linking claim.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on February 13, 2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2 and 5 are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Pulugurtha et al (U.S. 2022/0077320).
Regarding claim 1. Pulugurtha et al discloses a semiconductor device (FIG 6) comprising:
A bit line structure (FIG. 6, item 12; [0036]) extending in a first horizontal direction (FIG. 2, item X);
a vertical pattern (FIG. 6, item 18 on left side) on the bit line structure (FIG. 6, item 12) and including a first source/drain region (FIG. 6, item 22), a second source/drain region (FIG. 6, item 26) at a height higher ([0017]) than a height ([0017]) of the first source/drain region (FIG. 6, item 26), and a vertical channel region (FIG. 6, item 24) between the first (FIG. 6, item 22) and second (FIG. 6, item 26) source/drain regions ([0017]);
a front gate structure (FIG. 6, items 32 and 30 on left side) facing a first side surface (FIG. 6, item 18 left side surface) of the vertical pattern (FIG. 6, item 18 on left side); and
a back gate structure (FIG. 6, item 32 on right side) facing a second side surface (FIG. 6, item 18 right side surface) of the vertical pattern (FIG. 6, item 18 on left side) and extending ([0038]) in a second horizontal direction (FIG. 2, item Y) intersecting the first horizontal direction (FIG. 2, item X), the second side surface (FIG. 6, item 18 right side surface) of the vertical pattern (FIG. 6, item 18) being opposite to the first side surface (FIG. 6, item 18 left surface) of the vertical pattern (FIG. 6, item 18),
wherein the front gate structure (FIG. 6, items 32 and 30 on left side) includes: a gate electrode (FIG. 6, item 32 on left side) on the first side surface (FIG. 6, item 18 left side surface) of the vertical pattern (FIG. 6, item 18 on left side); and a gate dielectric layer (FIG. 6, item 30 on left side), wherein at least a portion of the gate dielectric layer (FIG. 6, item 30 on left side) is positioned between the vertical pattern (FIG. 6, item 18 on left side) and the gate electrode (FIG. 6, item 32 on left side);
wherein the back gate structure (FIG. 6, item 32 on right side) includes:
a back gate electrode (FIG. 6, item 32 on right side) on the second side surface (FIG. 6, item 18 right side surface) of the vertical pattern (FIG. 6, item 18 on left side); and
a dielectric structure (FIG. 6, item 84) including a portion (FIG. 6, item 84) between the vertical pattern (FIG. 6, item 18 on left side) and the back gate electrode (FIG. 6, item 32 on right side); and
wherein the dielectric structure (FIG. 6, item 84) includes an air gap (FIG. 6, item 92; [0053]) within the dielectric structure (FIG. 6, item 84), the air gap (FIG. 6, item 92) being located between (FIG. 6, shows item 92 is between item 18 on the left side and item 32 on right side) the vertical channel region (FIG. 6 item 18 on the left side) and the back gate electrode (FIG. 6, item 32 on right side),
wherein the bit line structure (FIG. 6, item 12; [0036]) is in contact ([0036]) with a lower surface ([0036]) of the first source/drain region (FIG. 6, item 22) and is spaced apart ([0036]) from the gate electrode (FIG. 6, item 32 on left side) and the back gate electrode (FIG. 6, item 32 on right side) in a vertical direction (FIG. 6, item Z; FIG 1 shows Z direction in reference to X direction).
Regarding claim 2. Pulugurtha et al discloses all the limitations of the semiconductor device of claim 1 above.
Pulugurtha et al further discloses wherein the dielectric structure (FIG. 6, item 84) comprises a first spacer (FIG. 6, item 80) defining at least one side of the air gap (FIG. 6, item 92).
Regarding claim 5. Pulugurtha et al discloses all the limitations of the semiconductor device of claim 2 above.
Pulugurtha et al further discloses wherein the first spacer comprises at least one of SiO, SiN, SiOC, SiON, SiCN, SiOCN, SiOCH, or SiOF ([0046]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 11, 27 and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Pulugurtha et al (U.S. 2022/0077320) as applied to claim 1 above, and further in view of Oh (U.S. 2016/0181377).
Regarding claim 11. Pulugurtha et al discloses all the limitations of the semiconductor device of claim 1 above.
Pulugurtha et al fails to explicitly disclose wherein the back gate structure includes a second auxiliary structure below the back gate electrode, wherein the second auxiliary structure defines a lower surface of the air gap.
However, Oh teaches wherein the back gate structure (FIG. 3, item 111A; [0065] i.e. the semiconductor device 100 is applied to a DRAM, a memory cell may include the gate structures 111A) includes a second auxiliary structure (FIG. 3, item 112 and 113) below the back gate electrode (FIG. 3, item 115; [Abstract], i.e. the gate electrode includes a first work function liner), wherein the second auxiliary structure (FIG. 3, item 113) defines ([0040], i.e. first work function liner 113 may be positioned under the air gap 117) a lower surface of the air gap (FIG. 3, item117; [0035]).
Since Pulugurtha et al and Oh teach vertical transistors, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semiconductor device as disclosed to modify Pulugurtha et al with the teachings of wherein the back gate structure includes a second auxiliary structure below the back gate electrode, wherein the second auxiliary structure defines a lower surface of the air gap as disclosed by Oh. The use of a gate structure with a first work function liner may be positioned under the air gap in Oh provides for refresh characteristic of the DRAM may be improved (Oh, [0065]).
Regarding claim 27. Pulugurtha et al discloses all the limitations of the semiconductor device of claim 1 above.
Pulugurtha et al fails to explicitly disclose wherein the air gap directly contacts the back gate electrode.
However, Oh teaches wherein the air gap (FIG. 3, item 117; [0046]) directly contacts ([0046]; i.e The air gap 117 may be positioned between the second work function liner 115 and the second junction region 118) the back gate electrode (FIG. 3, item 115).
Since Pulugurtha et al and Oh teach vertical transistors, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semiconductor device as disclosed to modify Pulugurtha et al with the teachings of wherein the air gap directly contacts the back gate electrode as disclosed by Oh. The use of the air gap may be positioned between the second work function liner and the second junction region in Oh provides suppressing Gate-induced drain leakage (GIDL) (Oh, [0063]).
Regarding claim 28. Pulugurtha et al discloses all the limitations of the semiconductor device of claim 1 above.
Pulugurtha et al further discloses wherein the air gap (FIG. 6, item 92; [0053]) is a first air gap (FIG. 6, item 92; [0053]).
Pulugurtha et al fails to explicitly disclose the dielectric structure includes a second air gap within the dielectric structure
the first and second air gaps are located on opposite sides of the back gate electrode.
However, Oh teaches the dielectric structure (FIG. 3, item 110 in items 211a and 211b) includes a second air gap (FIG. 3, item 117 in item 211B; [0046]) within the dielectric structure (FIG. 3, item 115 and 116 in items 211A and 211B)
the first (FIG. 3, item 117 in item 211A) and second (FIG. 3, item 117 in item 211B) air gaps ([0046]) are located on opposite ([0040]) sides of the back gate electrode (FIG. 3, item 115)
Since Pulugurtha et al teach vertical transistors, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semiconductor device as disclosed to modify Pulugurtha et al with the teachings of the dielectric structure includes a second air gap within the dielectric structure the first and second air gaps are located on opposite sides of the back gate electrode as disclosed by Oh. The use of the air gap may be positioned between the second work function liner and the second junction region in Oh provides for suppressing Gate-induced drain leakage (GIDL) (Oh, [0063]).
Claims 1-4, 6, 8-10, 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Basker et al (U.S. 2017/0330965), and Pulugurtha et al (U.S. 2022/0077320).
Regarding claim 1. Basker et al discloses a semiconductor device (FIG. 4 and 10) comprising:
A bit line structure extending in a first horizontal direction;
a vertical pattern (FIG. 10, items 1002 and 204; [Abstract]) on the bit line structure and including a first source/drain region ([Abstract]), a second source/drain region (FIG. 10, item 1002) at a height higher than a height of the first source/drain region ([Abstract]), and a vertical channel region (FIG. 10, item 204) between the first and second source/drain regions ([Abstract]; a vertical channel fin directly on a bottom source/drain region. A top source/drain region is formed directly on a top surface of the vertical channel fin);
a front gate structure (FIG. 4 and 10, item 406 on left side) facing a first side surface of the vertical pattern (FIG. 10, items 1002 and 204; [Abstract]); and
a back gate structure (FIG. 4 and 10, item 406 and 602 on right side) facing a second side surface of the vertical pattern (FIG. 10, items 1002 and 204; [Abstract]) and extending in a second horizontal direction intersecting the first horizontal direction, the second side surface of the vertical pattern (FIG. 10, items 1002 and 204; [Abstract]) being opposite to the first side surface of the vertical pattern (FIG. 10, items 1002 and 204; [Abstract]),
wherein the front gate structure (FIG. 4 and 10, item 406 on left side) includes: a gate electrode (FIG. 4 and 10, item 404 on left side) on the first side surface of the vertical pattern ([Abstract]); and a gate dielectric layer (FIG. 4 and 10, item 402 on left side), wherein at least a portion of the gate dielectric layer (FIG. 4 and 10, item 402 on left side) is positioned between the vertical pattern (FIG. 10, items 1002 and 204; [Abstract]) and the gate electrode (FIG. 4 and 10, item 404 on left side);
wherein the back gate structure (FIG. 10, item 406 on right side) includes:
a back gate electrode (FIG. 4 and 10, item 404 and 602 on right side) on the second side surface of the vertical pattern (FIG. 10, items 1002 and 204; [Abstract]); and
a dielectric structure (FIG. 4 and 10, item 402, 802, 804 on right side) including a portion (FIG. 4 and 10, item 402 on the right) between the vertical pattern (FIG. 10, items 1002 and 204; [Abstract]) and the back gate electrode (FIG. 4 and 10, item 404 on right side); and
wherein the dielectric structure (FIG. 4 and 10, item 402, 802, 804 on right side) includes an air gap (FIG.10, item 804) within the dielectric structure (FIG. 4 and 10, item 402, 802, 804 on right side) .
Basker et al fails to explicitly disclose
A bit line structure extending in a first horizontal direction;
vertical pattern on the bit line structure
a back gate structure extending in a second horizontal direction intersecting the first horizontal direction,
the air gap being located between the vertical channel region and the back gate electrode,
wherein the bit line structure is in contact with a lower surface of the first source/drain region and is spaced apart from the gate electrode and the back gate electrode in a vertical direction.
However Pulugurtha et al teaches A bit line structure (FIG. 6, item 12; [0036]) extending in a first horizontal direction (FIG. 2, item X);
a vertical pattern (FIG. 6, item 18 on left side) on the bit line structure (FIG. 6, item 12)
the back gate structure (FIG. 6, item 32 on right side) extending ([0038]) in a second horizontal direction (FIG. 2, item Y) intersecting the first horizontal direction (FIG. 2, item X), the second side surface (FIG. 6, item 18 right side surface) of the vertical pattern (FIG. 6, item 18) being opposite to the first side surface (FIG. 6, item 18 left surface) of the vertical pattern (FIG. 6, item 18),
the air gap (FIG. 6, item 92) being located between (FIG. 6, shows item 92 is between item 18 on the left side and item 32 on right side) the vertical channel region (FIG. 6 item 18 on the left side) and the back gate electrode (FIG. 6, item 32 on right side),
wherein the bit line structure (FIG. 2, item 12; [0036]) is in contact ([0036]) with a lower surface ([0036]) of the first source/drain region (FIG. 6, item 22) and is spaced apart ([0036]) from the gate electrode (FIG. 6, item 32 on left side) and the back gate electrode (FIG. 6, item 32 on right side) in a vertical direction (FIG. 6, item Z; FIG 1 shows Z direction in reference to X direction).
Since Basker et al and Pulugurtha et al teach vertical transistors, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semiconductor device as disclosed to modify Basker with the teachings of A bit line structure extending in a first horizontal direction; vertical pattern on the bit line structure the back gate structure extending in a second horizontal direction intersecting the first horizontal direction, the air gap being located between the vertical channel region and the back gate electrode , wherein the bit line structure is in contact with a lower surface of the first source/drain region and is spaced apart from the gate electrode and the back gate electrode in a vertical direction as disclosed by Pulugurtha et al. The use of the transistor 20 is shown to be provided between the conductive structure 12 and a storage element 40. The lower source/drain regions 22 is electrically coupled with the conductive structure 12, and the upper source/drain region 26 is electrically coupled with the storage element 40. In operation, the transistor 20 may be utilized as an access device between the conductive structure 12 and the storage element 40. The conductive structure 12 may correspond to a digit line (sense line, bitline) extending along the plane of the cross-section of FIG. 1, and the conductive gating material 32 may be part of a wordline (access line) 44 extending in and out of the plane of the cross-section of FIG. 1. in Pulugurtha et al provides for develop improved transistors (Pulugurtha et al, [0004]).
Regarding claim 2. Basker et al, and Pulugurtha et al discloses all the limitations of the semiconductor device of claim 1 above.
Basker et al further discloses wherein the dielectric structure (FIG. 4 and 10, item 402, 802, 804 on right side) comprises a first spacer (FIG. 10, item 802) defining at least one side of the air gap (FIG. 10, item 804).
Regarding claim 3. Basker et al, and Pulugurtha et al discloses all the limitations of the semiconductor device of claim 2 above.
Basker et al further discloses wherein the first spacer (FIG. 10, item 802) includes a material ([0045]) different ([0045],[0036]) from a material of the gate dielectric layer (FIG. 4 and 10, item 402 on left side; [0036]).
Regarding claim 4. Basker et al, and Pulugurtha et al discloses all the limitations of the semiconductor device of claim 3 above.
Basker et al further discloses wherein the gate dielectric layer comprises at least one of SiO, HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, or A12O3 ([0036]).
Regarding claim 6. Basker et al, and Pulugurtha et al discloses all the limitations of the semiconductor device of claim 2 above.
Basker et al further discloses wherein the first spacer (FIG. 10, item 802) includes a vertical extension portion (FIG. 10, item 802 next to item 1002) between the air gap (FIG. 10, item 804) and the vertical pattern (FIG. 10, items 1002 and 204; [Abstract]) and a horizontal extension portion (FIG. 10, item 802 contacting top of item 406 on right) extending from an upper end of the vertical extension portion (FIG. 10, item 802 next to item 1002) toward the back gate electrode (FIG. 4 and 10, item 404 and 602 on right side), wherein the horizontal extension portion (FIG. 10, item 802 contacting top of item 406 on right) is in contact with the back gate electrode (FIG. 4 and 10, item 404 and 602 on right side).
Regarding claim 8. Basker et al, and Pulugurtha et al discloses all the limitations of the semiconductor device of claim 2 above.
Basker et al further discloses wherein a width (FIG. 10, top and bottom of item 804) of the air gap (FIG. 10, item 804) is greater (FIG. 10, shows a width of item 804 is greater than a thickness of item 802) than a thickness (FIG. 10, shows thickness of item 802) of the first spacer (FIG. 10, item 802), and the width (FIG. 10, top and bottom of item 804) of the air gap (FIG. 10, item 804) is a distance (FIG. 10, top and bottom of item 804) between both sides (FIG. 10, top and bottom of item 804) of the air gap (FIG. 10, item 804)
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Regarding claim 9. Basker et al, and Pulugurtha et al discloses all the limitations of the semiconductor device of claim 1 above.
Basker et al further discloses wherein the back gate structure (FIG. 4 and 10, item 406 and 602 on right side) includes a first auxiliary structure (FIG. 10, item 802 contacting top of item 602 on right) on the back gate electrode (FIG. 4 and 10, item 404 and 602 on right side) and the dielectric structure (FIG. 4 and 10, item 402, 802, 804 on right side), and the vertical pattern (FIG. 10, items 1002 and 204; [Abstract]) has a portion (FIG. 10, items 1002) extending on a side surface (FIG. 10, item 802) of the first auxiliary structure (FIG. 10, item 802 contacting top of item 602 on right) along a side surface (FIG. 4 and 10, item 402 on right side) of the dielectric structure (FIG. 4 and 10, item 402, 802, 804 on right side).
Regarding claim 10. Basker et al, and Pulugurtha et al discloses all the limitations of the semiconductor device of claim 9 above.
Basker et al further discloses wherein the front gate structure (FIG. 4 and 10, item 406 on left side) comprises a gate capping layer (FIG. 10, annotated item 802 above item 404 to right of item 602 on left) on the gate electrode (FIG. 4 and 10, item 404 on left side), and a lower surface of the first auxiliary structure (FIG. 10, item 802 contacting top of item 602 on right) is at substantially a same height ([as directed to applicant’s elected species I, FIG. 3], FIG. 10 shows auxiliary structure is substantially same height of the gate capping layer) as or at a height lower than a lower surface of the gate capping layer (FIG. 10, annotated item 802 above item 404 to right of item 602 on left).
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Regarding claim 15. Basker et al, and Pulugurtha et al discloses all the limitations of the semiconductor device of claim 1 above.
Basker et al further discloses wherein an upper surface of the first source/drain region (FIG. 10, item 102) of the vertical pattern is on a same height as or at a height lower (FIG. 10, shows item 102 is lower than item 804) than a lower end (FIG. 10, lower end item 804) of the air gap (FIG. 10, item 804)
Regarding claim 16. Basker et al, and Pulugurtha et al discloses all the limitations of the semiconductor device of claim 1 above.
Basker et al further discloses wherein a lower surface (lower surface of item 1002) of the second source/drain region (FIG. 10, item 1002) of the vertical pattern (FIG. 10, item 1002, 204, 102) is located on a same height as ([as directed to applicant’s elected species I, FIG. 3], shows a lower surface of item 1002 is at the same height of an upper end of item 804) as or at a height higher than an upper end (FIG. 10, upper end of item 804) of the air gap (FIG. 10, item 804).
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Response to Arguments
Applicant's arguments filed April 6, 2026 have been fully considered but they are not persuasive.
On pages 3-5 of applicant’s remarks, applicant appears to argue that Pulugurtha’s FIG. 5 fails to disclose the amended claim limitations of claim 1.
Examiner respectfully points out that FIG. 5 of Pulugurtha et al was not used in the current rejection and that Pulugurtha et al FIG. 6 discloses applicant’s amended claim 1 limitations.
Conclusion
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/S.E.B./ Examiner, Art Unit 2815 /JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815
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