DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. This Non-Final office action is in response to application 18/178,463, application filed on 03/03/2023. Claims 1-20 are currently pending in this application.
Claim Rejections - 35 USC § 103
3. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
4. Claim(s) 1, 3-4 and 6-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rabinovitch et al. (US PG Pub No. 2016/0217235) in view of Huben et al. (US PG Pub No. 2008/0276144).
5. With respect to independent claim 1, Rabinovitch teaches:
An emulation system (emulation of circuits, Abstract; emulator and emulation environment, para 27-30) comprising:
emulator hardware for emulating a circuit design (logic circuits included in the emulator, para 38; emulator is a hardware system for emulating a DUT circuit, para 43; DUT made up of signals and logic circuits, para 29), including one or more emulation processors for modeling user design circuits of a netlist for the circuit design (see emulator processor; emulator may contain a hardware processor, para 119; netlist maps to logic circuit included in the emulator, para 38), and one or more physical binary memories for modeling user design memories of the netlist (see two-state semantic binary circuitry, para 55, modeling to convert to multi-state semantic circuit from netlist design, para 54-58); and
a computing processor (see computing processor, para 115-120) configured to:
identify, in the user design memories of the netlist, a user ternary memory [Examiner’s Note: For purposes of examination, Examiner interprets “ternary memory” as a multi-state or four state memory] to be modeled using a physical binary memory (see two-state semantic binary circuitry, para 55, modeling to convert to multi-state semantic circuit from netlist design, para 54-58; conversion of two state binary circuit into modeled four-state circuit, para 25-35).
Rabinovitch appears to be silent regarding:
instantiate a wrapper for modeling the user ternary memory, the wrapper includes instrumentation logic configured to perform one or more logical transformations of a ternary interface signal to model the user ternary memory,
wherein the user ternary memory is modeled using a combination of the instrumentation logic of the wrapper and a portion of the netlist for the physical binary memory.
However, Huben teaches:
instantiate a wrapper for modeling the user ternary memory (instantiates components for ternary model and wrapper, para 80-85), the wrapper includes instrumentation logic configured to perform one or more logical transformations of a ternary interface signal to model the user ternary memory (see wrapper schematic which includes design components that comprise the common logic block, para 67; see ternary model instantiated by wrapper schematic, para 80),
wherein the user ternary memory is modeled using a combination of the instrumentation logic of the wrapper and a portion of the netlist for the physical binary memory (wrapper schematic instantiating components, building ternary models with logic based on interfaces defined by netlist, para 80-82, 92-94).
It would have been obvious to one of ordinary skill in the art before the time of the invention to have incorporated Huben’s ternary memory wrapper into the invention of Rabinovitch for at least the following reason(s): Huben supports modeling and logical equivalence testing in DUT environments, like the one taught in Rabinovitch, and offers a significant improvement over traditional verification methods related to DUTs.
6. With respect to claim 3, while Rabinovitch appears to be silent regarding the limitations of claim 3 below, Huben teaches:
wherein the computing processor is further configured to determine, based upon the netlist, one or more ternary memory functions to be modeled at the user ternary memory (see ternary models modeling latches and design components, para 80), and
wherein the computing processor instantiates the wrapper according to the one or more ternary memory functions (see processor instantiating components, models built with wrapper schematic, para 81).
(For motivation to combine references, pleases see rejection of claim 1).
7. With respect to claim 4, Rabinovitch teaches:
wherein the user ternary memory is configured to model, according to the instrumentation logic of the wrapper, the one or more user ternary memory functions in response to an unknown logic state occurring at a port or memory location of the user ternary memory being modeled (see unknown state represented by corresponding memory address, see unknown state in four state semantic, para 30-35).
8. With respect to claim 6, Rabinovitch teaches:
wherein a tag bit stored in a tag memory for the user ternary memory being modeled indicates whether a particular memory location in the user ternary memory includes an unknown logic state (see identifying unknown states, para 27-32; enabling representation of an unknown state, para 29; see second bit that indicates/identifies whether the state is an unknown state, para 30-31).
9. With respect to claim 7, while Rabinovitch appears to be silent regarding the limitations of claim 3 below, Huben teaches:
wherein the computing processor is further configured to determine one or more wrapper parameters for instantiating the wrapper based upon the netlist (see instantiating wrapper, 80, 97), wherein the computing processor instantiates the wrapper according to the one or more wrapper parameters (see instantiating components of wrapper, see parameters of wrapper, para 75-83, 88-90).
(For motivation to combine references, pleases see rejection of claim 1).
10. With respect to claim 8, Rabinovitch teaches:
wherein, when determining the one or more wrapper parameters, the computing processor is further configured to:
identify one or more memory dimensions for at least one of the user ternary memory to be modeled or the physical binary memory (see wrapper schematic which includes design components that comprise the common logic block, para 67; see ternary model instantiated by wrapper schematic, para 80), wherein the instrumentation logic of the wrapper is configured to perform the one or more logic transformations according to the one or more memory dimensions (see logic conversion transformation for memories, para 60-63).
11. With respect to claim 9, Rabinovitch teaches:
wherein, when determining the one or more wrapper parameters, the computing processor is further configured to:
identify, based upon the netlist, one or more memory ports of the user ternary memory to be modeled, wherein the instrumentation logic of the wrapper is configured to perform the one or more logic transformations according to the one or more memory ports (see wrapper schematic which includes design components that comprise the common logic block, para 67; see ternary model instantiated by wrapper schematic, para 80; see logic conversion transformation for memories, para 60-63; see unknown state represented by corresponding memory address, see unknown state in four state semantic, para 30-35; see identifying unknown states, para 27-32; enabling representation of an unknown state, para 29; see second bit that indicates/identifies whether the state is an unknown state, para 30-31).
12. With respect to independent claim 10, Rabinovitch teaches:
An emulation system (emulation of circuits, Abstract; emulator and emulation environment, para 27-30) comprising:
emulator hardware for emulating a circuit design that operates with an unknown logic state (see emulation of circuits and representation of unknown states of signals, Abstract; logic circuits included in the emulator, para 38; emulator is a hardware system for emulating a DUT circuit, para 43; DUT made up of signals and logic circuits, para 29), including one or more emulation processors for modeling user design circuits of a netlist for the circuit design (see emulator processor; emulator may contain a hardware processor, para 119; netlist maps to logic circuit included in the emulator, para 38), and
a plurality of physical binary memories for modeling user design memories of the netlist (see two-state semantic binary circuitry, para 55, modeling to convert to multi-state semantic circuit from netlist design, para 54-58); and
a computing processor configured to:
identify, in the user design memories of the netlist, a user ternary memory to be modeled using a physical binary memory (see two-state semantic binary circuitry, para 55, modeling to convert to multi-state semantic circuit from netlist design, para 54-58; conversion of two state binary circuit into modeled four-state circuit, para 25-35).
Rabinovitch appears to be silent regarding:
instantiate a wrapper for modeling the user ternary memory, the wrapper includes instrumentation logic configured to perform one or more logical transformations of a ternary interface signal to model the user ternary memory,
wherein the user ternary memory is modeled using a combination of the instrumentation logic of the wrapper and a portion of the netlist for the physical binary memory.
However, Huben teaches:
instantiate a wrapper for modeling the user ternary memory (instantiates components for ternary model and wrapper, para 80-85), the wrapper includes instrumentation logic configured to perform one or more logical transformations of a ternary interface signal to model the user ternary memory (see wrapper schematic which includes design components that comprise the common logic block, para 67; see ternary model instantiated by wrapper schematic, para 80),
wherein the user ternary memory is modeled using a combination of the instrumentation logic of the wrapper and a portion of the netlist for the physical binary memory (wrapper schematic instantiating components, building ternary models with logic based on interfaces defined by netlist, para 80-82, 92-94).
It would have been obvious to one of ordinary skill in the art before the time of the invention to have incorporated Huben’s ternary memory wrapper into the invention of Rabinovitch for at least the following reason(s): Huben supports modeling and logical equivalence testing in DUT environments, like the one taught in Rabinovitch, and offers a significant improvement over traditional verification methods related to DUTs.
13. With respect to claim 11, Rabinovitch teaches:
wherein the emulation hardware includes a tag flop associated with the memory location of the user ternary memory, and wherein the tag flop indicates that the memory location of the user ternary memory is valid when the tag flop is asserted (see identifying unknown states, para 27-32; enabling representation of an unknown state, para 29; see second bit that indicates/identifies whether the state is an unknown state, para 30-31); and
wherein the instrumentation logic of one or more wrappers determines whether the memory location is valid based upon the flop device (see wrapper schematic which includes design components that comprise the common logic block, para 67; see ternary model instantiated by wrapper schematic, para 80; see logic conversion transformation for memories, para 60-63; see unknown state represented by corresponding memory address, see unknown state in four state semantic, para 30-35; see identifying unknown states, para 27-32; enabling representation of an unknown state, para 29; see second bit that indicates/identifies whether the state is an unknown state, para 30-31).
Allowable Subject Matter
14. Claims 2, 5 and 12-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
15. With respect to claim 2, the prior art made of record fails to teach the combination of steps recited in claim 2, including the following particular combination of steps as recited in claim 2, as follows:
wherein the computing processor is further configured to merge the instrumentation logic of the wrapper with netlist logic of the netlist by including the instrumentation logic of the wrapper around a portion of the netlist logic for the physical binary memory to model the user ternary memory.
16. With respect to claim 5, the prior art made of record fails to teach the combination of steps recited in claim 5, including the following particular combination of steps as recited in claim 5, as follows:
wherein the user ternary memory is configured to output, according to the instrumentation logic of the wrapper, a warning in response to an unknown logic state occurring at the user ternary memory.
17. With respect to claim 12, the prior art made of record fails to teach the combination of steps recited in claim 12, including the following particular combination of steps as recited in claim 12, as follows:
wherein, and when executing the memory corruption function, the instrumentation logic is configured to de-assert the flop device in response to an unknown logic state occurring in memory content or a target address during a memory-read function.
18. With respect to claim 13, the prior art made of record fails to teach the combination of steps recited in claim 13, including the following particular combination of steps as recited in claim 13, as follows:
wherein, and when executing the memory corruption function, the instrumentation logic is configured to de-assert the flop device in response to an unknown logic state occurring during a memory-write function.
19. With respect to claim 14, the prior art made of record fails to teach the combination of steps recited in claim 14, including the following particular combination of steps as recited in claim 14, as follows:
wherein, and when executing the memory corruption function, the instrumentation logic is configured to:
detect a condition involving unknown states; and de-assert a plurality of flop devices corresponding to a plurality of memory locations of a plurality of user ternary memories in response to the condition.
20. With respect to claim 15 (and claims 16-20 which depend therefrom), the prior art made of record fails to teach the combination of steps recited in claim 15, including the following particular combination of steps as recited in claim 15, as follows:
wherein the plurality of physical binary memories of the emulator hardware include a tag memory configured to store one or more tags associated with one or more memory locations in one or more user ternary memories, wherein a value of a tag corresponds to the value of a key applied to the memory location; and wherein the instrumentation logic of one or more wrappers is further configured to determine whether the memory location is valid based upon the tag associated with the memory location in the user ternary memory.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUCHIN PARIHAR whose telephone number is (703)756-1970. The examiner can normally be reached on M-F 8am-5pm.
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/SUCHIN PARIHAR/
Primary Examiner, Art Unit 2851
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