DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on March 9, 2026 has been entered.
Response to Arguments
Applicant’s amendments necessitated the shift in grounds of rejection detailed below. The shift in grounds of rejection renders Applicant’s arguments moot. Lii et al. ( US-20100314756-A1l Lii ) discloses a connection feature where a buffer layer separates it from the equivalent of the claimed second insulating layer.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “ wherein the first metal pattern and the solder pattern are spaced apart from the second insulating layer. “ must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 20-21 recites the limitation "a second insulating layer". There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 5-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. (US 20190057931 A1;Hsu) in view of Lii et al. ( US-20100314756-A1l Lii ).
Regarding claim 1, Hsu discloses a semiconductor package comprising: a first semiconductor package (Fig. 28, 2710; ¶42); and a second semiconductor package (Fig. 28, 288bc/288c/288m; ¶42) disposed on the first semiconductor package, wherein the first semiconductor package comprises: a lower redistribution substrate (Fig. 28, 2255; ¶42); a connection substrate (Fig. 28, 191ab; ¶41) disposed on the lower redistribution substrate, wherein the connection substrate comprises a through hole (Fig. 28,location of 1301ac; ¶42), a first insulating layer (Fig. 28, 1610/150p/150p; ¶32) and a through via (Fig. 28, 1511p; ¶32 equivalent to 1511p-5113p of Fig. 18) penetrating the first insulating layer; a lower semiconductor chip (Fig. 28, 1301ac; ¶42) disposed in the through hole; a connection layer (Fig. 25, 191a1,191a2,191a3; ¶37 defined in figure 18) disposed between the connection substrate and the lower redistribution substrate, wherein the connection layer comprises a first metal pattern (Fig. 18, 1511p-1513b; ¶34-35) and a solder pattern (Fig. 18, 1511ip-1513ip; ¶34-35) disposed on the first metal pattern; a first molding layer (Fig. 25, 2410; ¶38) disposed on the lower semiconductor chip and the connection substrate; and an upper redistribution substrate (Fig. 28, 288b; ¶42) disposed on the first molding layer, wherein the second semiconductor package comprises: a package substrate ( Fig. 29, not labeled but can be seen on bottom of chip 288; ¶42); an upper semiconductor chip (Fig. 29, 288c; ¶42) disposed on the package substrate; and a second molding layer (Fig. 29, 288m; ¶42) disposed on the package substrate and the upper semiconductor chip , and wherein the lower redistribution substrate comprises: a plurality of lower redistribution patterns; (Fig. 25, 2210r1; ¶36) and a second insulating layer disposed between uppermost ones of the plurality of the lower redistribution patterns (Fig. 28, 2210r1; ¶36) adjacent to each other in a first direction, but is silent on wherein the first metal pattern and the solder pattern are spaced apart from the second insulating layer..
The claim is written broadly enough so that the second redistribution layer 288bc can also be the package substrate.
Solder patterns 191a1-191a3 correspond to the solder patterns of Figure 18, comprising 1511b-1513b, unlabeled intervening layer, and 1511ip-1513ip in paragraph 34-35. Applicant’s solder is analogous to 1511ip-1513ip.
It is well known in the art to use metal for connection structures, interconnects, pads, and solder. However, Hsu is silent on the connection structure using metal.
Lii discloses connection structure comprising a solder bump (Fig. 1, 50; ¶20) on a first metal layer (Fig. 1, 40 Titanium; ¶18) and a second metal layer (Fig. 1, 48 Nickel; ¶18); and buffer layer (Fig. 1, 42; ¶17) separating the interconnection structure from an insulating layer (Fig. 1, 34; ¶17) that is on a lower interconnect substrate. (Fig. 1, 26; ¶18)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to utilize the connection structure configuration of Lii for making optimal electrical connections as is well known in the art.
Regarding claim 2, Hsu in view of Lii discloses the semiconductor package of claim 1, wherein the first metal pattern (Fig. 18, 1511p-1513b; ¶34-35 Hsu), the solder pattern (Fig. 18, 1511ip-1513ip; ¶34-35 Hsu), and the through via (Fig. 28, 1511p-5113p of 21 ¶32 Hsu) vertically overlap each other, and wherein the first insulating layer (Fig. 28, mold 1610/150p/150p ¶35 Hsu) and the first molding layer (Fig. 25, 2410; ¶38 polymer Hsu) comprise different materials from each other.
Regarding claim 5, Hsu in view of Lii discloses the semiconductor package of claim 1, wherein the first metal pattern (Fig. 18, 1511b-1513b; ¶34-35 Hsu) is disposed in contact with the lower redistribution pattern (Fig. 28, 2210r1; ¶36 electrical contact to 261b Hsu)
Regarding claim 6, Hsu in view of Lii discloses the semiconductor package of claim 5, wherein the second insulating layer (Fig. 25,2210p3; ¶36 Hsu) includes Ajinomoto build-up film (ABF).
Regarding claim 7, Hsu in view of Lii discloses the semiconductor package of claim 1, wherein the first insulating layer (Fig. 28, mold 1610/150p/150p ¶35 Hsu) overlaps (extends past the side surface from a higher plane) a side surface of the solder pattern. (Fig. 25, 191a1,191a2,191a3; ¶37 Hsu)
Claim(s) 3,8, and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. (US 20190057931 A1;Hsu) in view of Lii et al. ( US-20100314756-A1l Lii ), and further in view of Das et al. (US 20170092621 A1; Das).
Regarding claim 3, Hsu in view of Lii discloses the semiconductor package of claim 1, but is silent on wherein the first metal pattern includes nickel (Ni), and wherein the solder pattern includes tin (Sn) and/or a tin-silver alloy (Sn-Ag).
Das discloses a connection structure comprising a Ni-Au-Sn layer configuration. (Fig. 14, 450;¶170)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to utilize the metals of Das for making electrical connections as is well known in the art.
Regarding claim 8, Hsu in view of Lii discloses the semiconductor package of claim 1, wherein the connection layer (Fig. 25, 191a1,191a2,191a3; ¶37 Hsu) further includes a second metal (Fig. 18, unlabeled between 1512ip and 1512b Hsu) pattern, wherein the second metal pattern is disposed between the first metal pattern (Fig. 18, 1512b; ¶34-37 Hsu) and the solder pattern (Fig. 18, 1512ip; ¶37 Hsu), but is silent on and wherein the second metal pattern comprises gold (Au).
Das discloses a connection structure comprising a Ni-Au-Sn layer configuration. (Fig. 14, 450;¶170)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to utilize the metals of Das for making optimal electrical connections as is well known in the art.
Regarding claim 13, Hsu in view of Lii discloses the semiconductor package of claim 1, wherein the lower redistribution substrate (Fig. 28, 2255; ¶42 Hsu) comprises a lower redistribution pattern (Fig. 25, 2210r1; ¶36 Hsu), but is silent on and wherein the solder pattern, the first metal pattern, and the lower redistribution pattern comprise materials different from each other.
Das discloses a connection structure comprising a Ni-Au-Sn layer configuration. (Fig. 14, 450;¶170) electrically coupled to an aluminum contact.(Fig. 4, 442; ¶166)
Before the effective filing date of the invention one having ordinary skill in the art would be enabled to choose different conductive materials for the benefit of taking advantage of bonding, conductive, and thermal conductive characteristics.
Claim(s) 4 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. (US 20190057931 A1;Hsu) in view of Lii et al. ( US-20100314756-A1l Lii ), and further in view of Kang et al. (US 20200051907 A1; Kang).
Regarding claim 4, Hsu in view of Lii discloses the semiconductor package of claim 1, but is silent on wherein the first insulating layer includes polypropylene glycol (PPG).
Kang discloses a using PPG for an interconnect dielectric (Fig. 2, 220; ¶30) in package
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to use PPG as a matter of design choice when seeking a known material suitable for insulating and strength characteristics.
Regarding claim 9, Hsu in view of Lii discloses the semiconductor package of claim 1, but is silent on wherein a width of the through via measured in a first direction decreases and increases from an upper surface of the first insulating layer to a lower surface of the first insulating layer, wherein the through via has an hourglass shape in a cross-sectional view.
Kang discloses forming a through via having an hourglass shape. (Fig. 14, 113a; ¶114)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to change the shape of a through via as a matter of design choice. Because, where the only difference between the prior art and the claims is a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. MPEP 2144.04 IV A
Claim(s) 10, 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. (US 20190057931 A1;Hsu) in view of Lii et al. ( US-20100314756-A1l Lii ) and further in view of Kim (US 20220013498 A1; Kim).
Regarding claim 10, Hsu in view of Lii discloses the semiconductor package of claim 1, wherein a level of the upper surface of the through via (Fig. 28, 1511p; ¶32 equivalent to 1511p-5113p of Fig. 18 Hsu) is higher than a level of an upper surface of the first insulating layer; (Fig. 28, mold 1610 ¶35 Hsu) but is silent on and wherein an upper surface of the through via is exposed to an upper surface of the first molding layer.
Hsu discloses forming another dielectric layer on the mold layer that is exposed to the upper surface of the via. One of ordinary skill in the art could avoid this step by forming one molding layer.
Kim discloses a similar package configuration where the top surface of a substrate (Fig. 11,522/532; ¶120) through via (Fig. 11, 524/534; ¶120) is exposed to the top surface of a molding layer (Fig. 11, 502; ¶120) and coplanar.
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to utilize one molding layer to encompass the through via and wiring for the benefit of limiting process steps and material costs.
Regarding claim 11, Hsu in view of Das and Kim discloses the semiconductor package of claim 10, wherein the upper redistribution substrate (Fig. 28, 288b; ¶42 Hsu) comprises an upper redistribution pattern (Fig. 28, 288bc; ¶42 Hsu) , …and wherein the upper surface of the through via (Fig. 28, 1511p; ¶32 equivalent to 1511p-5113p of Fig. 18) is in contact (electrically) with the upper redistribution pattern.
Hsu is silent on wherein the first molding layer overlaps at least a portion of a side surface of an upper portion of the through via.
Kim discloses a similar package configuration where wherein the first molding layer (Fig. 11, 502; ¶120 Kim) overlaps at least a portion of a side surface of an upper portion of the through via (Fig. 11, 524/534; ¶120 Kim).
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to use a single mold layer surrounding the vias instead of a mold/dielectric combination to reduce material costs and deposition steps.
Claim(s) 14-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. (US 20190057931 A1;Hsu) in view of Lii et al. (US-20100314756-A1; Lii), Kim (US 20220013498 A1; Kim), and further in view of Kang et al. (US 20200051907 A1; Kang).
Regarding claim 14, Hsu discloses a semiconductor package comprising: a
lower redistribution substrate (Fig. 28, 2255; ¶142); a connection substrate (Fig. 28,
191ab; ¶41) disposed on the lower redistribution substrate, wherein the connection
substrate comprises a through hole (Fig. 28,location of 1301ac; ¶142), a first insulating
layer (Fig. 28, 1610/150p/150p; ¶32) , and a through via (Fig. 28, 1511p; ¶132 equivalent to 1511p-5113p of Fig. 18) penetrating the first insulating layer; a lower semiconductor chip (Fig. 28, 1301a; ¶137) disposed in the through hole, wherein the lower semiconductor chip comprises a lower chip body, a lower chip pad (Fig. 28, not labeled coupled to 151b; 137) disposed on a lower surface of the lower chip body, and a connection terminal (Fig. 28, 151b; 137) disposed under the lower chip pad; a connection layer (Fig. 25, 191a1, 191a2, 191a3; 137 defined in figure 18) disposed between the connection substrate and the lower redistribution substrate, wherein the connection layer comprises a first… pattern (Fig. 18, 1511p-1513b; ¶34-35), a second … pattern (not labeled between 1511p and 1511ip) disposed on the first metal pattern, and a solder pattern (Fig. 18, 1511ip-1513ip; ¶34-35) disposed on the second metal pattern; a molding layer (Fig. 25, 2410; ¶34-35) overlapping the lower semiconductor chip and the connection substrate; and an upper redistribution substrate (Fig. 28, 288b; ¶142) disposed on the molding layer, wherein a lower surface of the through via is in contact (electrical contact) with an upper surface of the solder
pattern, and wherein the solder pattern and the connection terminal comprise the same material. (in the same layer)
Hsu is silent on wherein the through via has a first width measured in a first
direction at a level of an upper surface of the first insulating layer and a second width
measured in the first direction at a level of a lower surface of the first insulating layer,
wherein the through via has a third width measured at a point inside the first insulating
layer, and wherein the third width is smaller than the first width and the second width. Also, it is well known in the art to use metal for connection structures, interconnects, pads, and solder. However, Hsu is silent on the connection structure
using metal. Hsu is silent on wherein a width of the solder pattern measured in the first direction is greater than a width of the first metal pattern measured in the first direction.
Applicant is claiming an hourglass shape and non-critical relative dimensions.
Kang discloses forming a through via having an hourglass shape. (Fig. 14, 113a; ¶14)
Before the effective filing date of the invention it would have been obvious to one
having ordinary skill in the art to change the shape of a through via as a matter of
design choice. Because, where the only difference between the prior art and the claims is a recitation of relative dimensions of the claimed device and a device having the
claimed relative dimensions would not perform differently than the prior art device, the
claimed device was not patentably distinct from the prior art device. MPEP 2144.04 IV A
Kim discloses a similar package configuration where the top surface of a
substrate (Fig. 11,522/532; 120) through via (Fig. 11, 524/534; ¶120) is exposed to the
top surface of a molding layer (Fig. 11, 502; ¶120) and coplanar.
Before the effective filing date of the invention it would have been obvious to one
having ordinary skill in the art to use a single mold layer instead of a mold/dielectric
combination to reduce material costs and deposition steps.
Lii discloses a connection structure comprising a first metal layer (Fig. 1, 40 Titanium; ¶18), a second metal layer (Fig. 1, 48 Nickel; ¶18), and a solder bump (Fig. 1, 50; ¶14), where a width of the solder bump is larger than a width of the first metal layer.
The applicant has not presented persuasive evidence in specification that the claimed relative widths of the solder and first metal pattern are for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed dimensions). Also, the applicant has not shown that the claimed dimensions produce a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art.
Therefore, before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to form a connection structure comprising a solder bump on a stack of metal layers, and to adjust the relative widths of the solder and first metal patterns to achieve optimal bonding strength and alignment using under bump metallization techniques. Also, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
MPEP 2144.04 (IV)(A)
Regarding claim 15, Hsu in view of Kang, Lii, Kim discloses the semiconductor package of claim 14, wherein the lower redistribution substrate (Fig. 25, 2255; ¶36 Hsu) further comprises: a plurality of lower redistribution patterns (Fig. 25, 2210r1; ¶36 Hsu); and a second insulating layer (Fig. 25,2210p3; ¶36 Hsu) disposed between uppermost ones of the plurality of the lower redistribution patterns adjacent to each other in the first direction, wherein the first metal pattern (Fig. 1, 40 Titanium; ¶18 Lii), the second metal pattern, (Fig. 1, 48 Nickel; ¶18 Lii) and the solder pattern (Fig. 1, 50; ¶14 Lii) are spaced apart (Fig. 1, by buffer 42; ¶17 Lii) from the second insulating layer. (Fig. 1, 34; ¶17 Lii)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in art to use the connection structure of Lii for making optimal electric connections using under bump technology.
Regarding claim 16, Hsu in view of Kang, Lii, Kim discloses the
semiconductor package of claim 15, wherein a lower surface (dotted line of 1511p Hsu) of the through via (Fig. 28, 1511p; ¶32 equivalent to 1511p-5113p of Fig. 18 Hsu) and a lower surface of the first insulating layer (Fig. 28, 1610; ¶32 Hsu) are coplanar with each other.
Regarding claim 17, Hsu in view of Kang, Lii, Kim discloses the
semiconductor package of claim 15, wherein the first metal pattern, (Fig. 1, 40 Titanium; ¶18 Lii), the second metal pattern, (Fig. 1, 48 Nickel; ¶18 Lii) and the solder pattern (Fig. 1, 50; ¶14 Lii), comprise materials different from each other, and wherein side surfaces of the first metal pattern, (Fig. 18, 1511p-1513b; ¶34-35 Hsu) side surfaces of the second metal pattern (not labeled between 1511p and 1511ip), and side surfaces of the solder pattern (Fig. 18, 1511ip-1513ip; ¶34-35 Hsu) are in contact with the molding layer. (Fig. 18,2410; ¶38 Hsu)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in art to use the connection structure of Lii for making optimal electric connections using under bump technology.
Regarding claim 18, Hsu in view of Kang, Lii, Kim discloses the
semiconductor package of claim 14, wherein the lower semiconductor chip (Fig. 28,
1301a; ||37 Hsu) comprises a lower chip body and a lower chip pad (Fig. 28, not labeled
coupled to 151b; 137 Hsu) disposed on a lower surface of the lower chip body, and wherein a level of a lower surface of the first insulating layer (Fig. 28, 1610; ¶32 Hsu) is lower than a level of a lower surface of the lower chip pad. (clear from drawings)
Claim(s) 20,21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. (US 20190057931 A1;Hsu) in view of Lii et al. (US-20100314756-A1; Lii), and further in view of Kang et al. (US 20200051907 A1; Kang).
Regarding claim 20, Hsu discloses a semiconductor package comprising: a lower redistribution substrate (Fig. 28, 2255; ¶42) comprising: a plurality of lower redistribution patterns (Fig. 25, 2210r1; ¶36); and a second insulating layer (Fig. 25,2210p3; ¶36 Hsu) disposed between uppermost ones of the plurality of the lower redistribution patterns adjacent to each other in the first direction; a lower semiconductor chip (Fig. 28, 1301a; ¶37) disposed on the lower redistribution substrate; a connection substrate (Fig. 28, 191ab; ¶41) surrounding the lower semiconductor chip, wherein the connection substrate comprises an insulating layer (Fig. 28, 1610; ¶32) having a through hole (Fig. 28,location of 1301ac; ¶42) and a through via (Fig. 28, 1511p; ¶32 equivalent to 1511p-5113p of Fig. 18) penetrating the insulating layer; a connection layer (Fig. 25, 191a1,191a2,191a3; ¶37 defined in figure 18) disposed between the connection substrate and the lower redistribution substrate; and a molding layer (Fig. 25, 2410; ¶38) disposed on the lower semiconductor chip, the connection substrate, and the connection layer, wherein the connection layer comprises metal patterns (Fig. 18, 1511p-1513b; ¶34-35) and a solder pattern (Fig. 18, 1511ip-1513ip; ¶34-35) disposed on the metal patterns which are sequentially stacked in a region vertically overlapping the through via of the connection substrate, wherein the metal patterns, the solder pattern, and the through via vertically overlap each other, (clear from cited figures)
Hsu is silent on wherein the metal patterns, the solder pattern, and the through via comprise materials different from each other, and wherein the through via has a shape of an hourglass in a cross-sectional view.
Kang discloses forming a through via having an hourglass shape. (Fig. 14, 113a; ¶114)
Also, it is well known in the art to use metal for connection structures, interconnects, pads, and solder. However, Hsu is silent on the connection structure using metal.
Lii discloses connection structure comprising a solder bump (Fig. 1, 50; ¶20) on a metal layers (Fig. 1, 40 Titanium/48 Nickel; ¶18);
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to utilize the connection structure configuration of Lii for making optimal electrical connections as is well known in the art. Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to change the shape of a through via as a matter of design choice. Because, where the only difference between the prior art and the claims is a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. MPEP 2144.04 IV A
Regarding claim 21, Hsu in view of Kang, Lii discloses the semiconductor package of claim 20, wherein the lower semiconductor chip (Fig. 28, 1301a; ¶37 Hsu) comprises a lower chip body and a lower chip pad (Fig. 28, not labeled coupled to 151b; ¶37 Hsu) disposed on a lower surface of the lower chip body, and wherein a level of a lower surface of the insulating layer (Fig. 28, 1610; ¶32 Hsu) is lower than a level of a lower surface of the lower chip pad. (clear from cited drawings)
Allowable Subject Matter
Claims 12, are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance, which paraphrases and summarizes the claimed invention without intending to be limiting, wherein the legally defined scope of the claimed invention is defined by the allowed claims themselves in view of the written description under 35 USC 112. This statement is not intended to necessarily state all the reasons for allowance or all the details why the claims are allowed and has not been written to specifically or impliedly state that all the reasons for allowance are set forth (MPEP 1302.14).
The cited art, including US-20160056103-A1, discloses molding layers surrounding connection substrates and embedded chips within through holes of the connection substrates. The art also disclose connection structures comprising metals and solder bumps that provide electrical connectivity between the connection substrate and a lower substrate. The art is silent on the following limitation in combination with the rest of the claimed limitations.
Regarding claim 12, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: " and wherein the first molding layer is spaced apart from the solder pattern. ”, as recited in Claim 12, with the remaining features.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAWRENCE C TYNES JR. whose telephone number is (571)270-7606. The examiner can normally be reached 9AM-5PM.
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/LAWRENCE C TYNES JR./Examiner, Art Unit 2899
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