DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s amendments to the claims 1, 6, 8, 9, 11 – 14, and 16 - 20 have been fully considered. Based on the cited prior arts Liaw, Tao, Chiu, Cheng and new grounds of rejections from Xie and Lee the claims 1-20 are rejected.
Response to Amendment
Applicant’s amendments to the specification, filed on 12/17/2025 have been fully considered and resolve the informalities of specification objections. The objection to the specification has been withdrawn.
Applicant’s amendments to the claims 11 and 17, filed on 12/17/2025 have been fully considered and resolve the informalities of claim objections. The objection to the claims has been withdrawn.
Applicant’s amendments with respect to claims 6, 8, 11, 12, 13, 16, and 19 filed on 12/17/2025 have been fully considered and resolve the issues of indefiniteness and lack of written description. The 35 U.S.C. 112(b) rejections of claims 6, 8, 11, 12, 13, 16, and 19 have been withdrawn. However, the amended claim 13 is objected to due to minor informalities.
Claim Objections
Claim 13 is objected to because of the following informalities:
Claim 13 recites “a front side Vdd power rail of
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 12 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 12 recites “wherein no vias within a perimeter of the logic block extend from a frontside of the semiconductor device to a backside of the semiconductor device, wherein the first frontside to backside signal via is outside the perimeter of the logic block, and wherein the second frontside to backside signal via is within the perimeter of the logic block.”
The limitation “wherein no vias within a perimeter of the logic block” and “wherein the second frontside to backside signal via is within the perimeter of the logic block” are indefinite.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 3 and 5 - 7 are rejected under 35 U.S.C. 103 as being unpatentable over Liaw (US20220336474A1; hereinafter Liaw) in view of Xie et al. (US10665669B1; hereinafter Xie).
Regarding Claim 1 (Currently Amended), Liaw discloses a semiconductor device (integrated circuit 10) comprising: a logic block (logic circuit 40), wherein the logic block comprises circuitry for one logic function of the semiconductor device (FIG. 1, [0021], [0022]);
a frontside to backside signal via (430, FIG. 5E reproduced below, [0065]) vertically aligned and directly connecting a first backside metal signal (222 wl, [0053]) to a first frontside metal signal (426, [0060]),
wherein the frontside to backside signal via (430) is only in an edge cell (422c) of the logic block, FIG. 5E, [0065].
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Liaw: FIG. 5E
Liaw discloses a first nanosheet transistor device 628a and second nanosheet transistor 628b, FIG. 6C, [0070]. Liaw does not disclose “a double diffusion break region arranged between a first nanosheet transistor device and a second nanosheet transistor device of the logic block; wherein a first gate structure of the first nanosheet transistor device wraps around ends of first channel nanosheets in the double diffusion break region, and a second gate structure of the second nanosheet transistor device wraps around ends of second channel nanosheets in the double diffusion break region.”
In a similar art, Xie discloses IC structures incorporating isolation and diffusion break elements [col.1, line 11].
Xie discloses: a double diffusion break region (194, FIG. 4 reproduced below, [col.9, line7]) arranged between a first nanosheet transistor device (nanosheet stack 200) and a second nanosheet transistor device (nanosheet stack 200) of the logic block (set of logic transistors in structure 100, FIG. 4, [col. 16, line 33]).
wherein a first gate structure (162) of the first nanosheet transistor device (200) wraps around ends of first channel nanosheets (210) in the double diffusion break region (194), FIG. 5 reproduced below, [col. 9, line 3, line 60].
and a second gate structure (162) of the second nanosheet transistor device (200) wraps around ends of second channel nanosheets (210) in the double diffusion break region (194), FIG. 5, [col. 9, line 3, line 60].
Xie (FIG. 5, [col. 9, line 60]) discloses nanosheet stacks 200 includes a plurality of semiconductor nanosheets 210 alternating with portions of gate region 162 filling space between each semiconductor nanosheet 210, indicating the gate structure wraps around ends of each channel nanosheet 210.
Xie [col. 9, line 3] discloses the diffusion break region 194 may horizontally separate a pair of upper surfaces U1, U2 of isolation layer 192 from each other, with each upper surface U1, U2 corresponding to one active layer 110A, 110B. Xie (FIG.4, [col. 9, line 14]) discloses diffusion break region 194 may extend upward from isolation layer 192 and may be integral with isolation layer 192, indicating the gate structures of the nanosheet transistor devices which wraps around ends of channel nanosheets 210 are in the double diffusion break region 194.
The combination of Liaw and Xie discloses: wherein the frontside to backside signal via (Liaw: 430, FIG. 5E, [0065]) passes through the double diffusion break region directly between the first gate structure and the second gate structure (Xie: double diffusion break region 194 between first gate structure 162 and second gate structure 162, FIG. 4, [col. 9, line 3, line 60]).
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Xie: FIGS. 4, 5
Xie discloses that a device as taught mitigates parasitic current leakage and improves performance [col. 1, line 25]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Liaw’s device in order to mitigate parasitic current leakage and improve performance as disclosed by Xie [col. 1, line 25].
Regarding Claim 2 (Original), The combination of Liaw and Xie discloses the semiconductor device according to claim 1.
Liaw discloses: wherein the logic block (400) comprises a set of circuit rows (memory cell array 402 has m rows by n columns for bit cells 102, FIG. 4, [0057]), a set of backside metal Vdd power rails (622 vdd, FIG. 6B, [0076]), a set of backside metal Vss power rails (622 vss, FIG. 6B, [0076]).
Regarding Claim 3 (Original), The combination of Liaw and Xie discloses the semiconductor device according to claim 2.
Liaw discloses: further comprising: each backside metal Vdd power rail (622 vdd, FIG. 6B) of the set of backside metal Vdd power rails is continuous with no breaks across the logic block; and each backside metal Vss power rail (622 vss, FIG. 6B) of the set of backside metal Vss power rails is continuous with no breaks across the logic block (600, FIG. 6B).
Liaw [0076] discloses the conductive routing lines 622 vdd and 622 vss are backside conductive routing lines connected to high-voltage source VDD and low-voltage source VSS respectively; and FIG. 6B shows them as continuous rails across the logic block, indicating the backside metal Vdd power rail and the frontside metal Vdd power rails are continuous with no breaks across the logic block.
Regarding Claim 5 (Original), The combination of Liaw and Xie discloses the semiconductor device according to claim 1.
Liaw discloses: further comprising: the logic block (40) comprises circuitry for a microprocessor device (system on chip (SOC) circuit with embedded memory circuits, [0022]).
Regarding Claim 6 (Currently Amended), The combination of Liaw and Xie discloses the semiconductor device according to claim 2.
Liaw discloses: wherein the set of circuit rows comprises 1000 circuit rows (FIG. 4, [0057]). Liaw discloses the memory circuit 400 includes a memory cell array 402 which includes m rows by n column where m is an integer corresponding to the number of rows, indicating that the set of circuit rows may comprise 1000 circuit rows.
Regarding Claim 7 (Original), The combination of Liaw and Xie discloses the semiconductor device according to claim 1.
Liaw discloses: further comprising: a set of front side Vdd power rails (218 vdd) and a set of front side Vss power rails (218 vss), FIG.7, [0080].
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Liaw in in view Xie, further in view of Tao et al. (US20230046117A1; hereinafter Tao).
Regarding Claim 4, The combination of Liaw and Xie discloses the semiconductor device according to claim 1.
The combination of Liaw and Xie does not disclose “wherein the frontside to backside signal via is a nano through silicon via (nTSV)”.
In a similar art, Tao discloses a method of producing an integrated circuit chip [0008].
The combination of Liaw and Tao disclose: wherein the frontside to backside signal via (Liaw: 430) is a nano through silicon via (nTSV), Tao: 24, FIG. 2n, [0005], [0052]. Tao [0005], [0030] discloses the formation of nano through silicon via connections (nTSV) to form interconnects in a method of producing an IC chip, indicating the frontside to backside signal via can be a nano through silicon via (nTSV).
Tao discloses that a semiconductor device as taught reduces interconnect congestion issues by enabling further scaling [0004]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Liaw and Xie’s device, in order to reduce interconnect congestion issues by enabling further scaling as disclosed by Tao [0004].
Claims 8, 9, and 15 - 17 are rejected under 35 U.S.C. 103 as being unpatentable over Liaw in view of Lee (US20220037307A1; hereinafter Lee).
Regarding Claim 8 (Currently Amended), Liaw discloses a semiconductor device (integrated circuit 10) comprising:
a logic block (logic circuit 40), wherein the logic block comprises circuitry for one logic function of the semiconductor device, FIG. 1, [0021], [0022];
a first frontside to backside signal via (430, FIG. 5E, [0065]) vertically aligned and directly connecting a first backside metal signal (222 wl, [0053]) to a first frontside metal signal (426, [0060]),
wherein the first frontside to backside signal via (430) is only in an edge cell (422c) of the logic block, FIG. 5E, [0065].
a second frontside to backside signal via (430, FIG. 5E, [0065]) vertically aligned and directly connecting a second backside metal signal (222 wl, [0053]) to a second frontside metal signal (426, [0060]).
Liaw discloses each edge cells 422 may include a word line tap structure 424, thereby a second frontside to backside signal via 430 is vertically aligned and directly connects a second backside metal signal to a second frontside metal signal.
Liaw does not disclose “a macro cell within the logic block.”
In a similar art, Lee discloses a semiconductor device with plurality of integrated circuits 20, wiring structure 30, and a plurality of TSV structures 40, FIG. 1A, [0025].
Lee discloses an operation (D130) of disposing a hard macro or a hard block in the first integrated circuit area and the second integrated circuit area of each of the semiconductor devices (e.g., stack 1, stack 2, . . . stack N), FIG. 10, [0076].
Lee discloses: a macro cell (hard macro) within the first logic block (first integrated circuit 20-1), FIG. 10, [0076].
The combination of Liaw and Lee disclose: wherein the second frontside to backside signal via (Liaw: 430, FIG. 5E, [0065]) is only in an edge cell (Liaw: 422c) of the macro cell (Lee: hard macro, [0076]).
Lee discloses that a device as taught increases communication speed of the semiconductor device [0080]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Liaw’s device in order to increase communication speed as disclosed by Lee [0080].
Regarding Claim 9, The combination of Liaw and Lee disclose the semiconductor device according to claim 8.
Liaw discloses a logic block (400) comprises a set of circuit rows (memory cell array 402 has m rows by n columns for bit cells 102, FIG. 4, [0057]),
Lee discloses forming a macro cell (hard macro) within the logic block (first integrated circuit 20-1), FIG. 10, [0077].
The combination of Liaw and Lee disclose: wherein the logic block comprises a set of circuit rows (Liaw: memory circuit 400 includes a memory cell array 402), wherein at least one circuit row of the set of circuit rows is interrupted by the macro cell (Lee: hard macro, FIG. 10, [0077]).
Lee FIG.10 discloses an operation D130 where hard macro is disposed in the semiconductor device. After that in operation D140 logic cells are placed in the integrated circuit area such that logic cells do not overlap the hard macro. Further in operation D150 hard macros and the logic cells are electrically connected for routing, thereby the hard macros are placed in a manner the row of logic cells are interrupted.
Lee discloses that a device as taught increases communication speed of the semiconductor device [0080]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Liaw’s device in order to increase communication speed as disclosed by Lee [0080].
Regarding Claim 15 (Original), The combination of Liaw and Lee disclose the semiconductor device according to claim 8.
Liaw discloses: further comprising: the logic block (40) comprises circuitry for a microprocessor device (system on chip (SOC) circuit with embedded memory circuits, [0022]).
Regarding Claim 16 (Currently Amended), The combination of Liaw and Lee discloses the semiconductor device according to claim 8.
Liaw discloses: further comprising: a set of circuit rows comprising 1000 circuit rows (FIG. 4, [0056]). Liaw discloses the memory circuit 400 includes a memory cell array 402 which includes m rows by n column where m is an integer corresponding to the number of rows, indicating that the set of circuit rows can comprise 1000 circuit rows.
Regarding Claim 17 (Currently Amended), The combination of Liaw and Lee discloses the semiconductor device according to claim 8.
Liaw discloses: further comprising: a set of front side Vdd power rails (218 vdd) and a set of front side Vss power rails (218 vss), FIG.7, [0080].
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Liaw in in view Lee, further in view of Tao.
Regarding Claim 14, The combination of Liaw and Lee discloses the semiconductor device according to claim 8.
The combination of Liaw and Lee does not disclose “wherein the frontside to backside signal via is a nano through silicon via (nTSV)”.
In a similar art, Tao discloses a method of producing an integrated circuit chip [0008].
The combination of Liaw and Tao disclose: wherein the frontside to backside signal via (Liaw: 430) is a nano through silicon via (nTSV), Tao: 24, FIG. 2n, [0005], [0052]. Tao [0005], [0030] discloses the formation of nano through silicon via connections (nTSV) to form interconnects in a method of producing an IC chip, indicating the frontside to backside signal via can be a nano through silicon via (nTSV).
Tao discloses that a semiconductor device as taught reduces interconnect congestion issues by enabling further scaling [0004]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Liaw and Lee’s device, in order to reduce interconnect congestion issues by enabling further scaling as disclosed by Tao [0004].
Claims 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Liaw in view of Lee, further in view of Chiu et al. (US20210343332A1; hereinafter Chiu).
Regarding Claim 10, The combination of Liaw and Lee discloses the semiconductor device according to claim 8.
Liaw discloses: wherein the logic block (400) comprises a set of circuit rows (memory cell array 402 has m rows by n columns for bit cells 102, FIG. 4, [0057]), a set of backside metal Vdd power rails (622 Vdd, FIG. 6B, [0076]), a set of backside metal Vss power rails (622 Vss, FIG. 6B, [0076]).
The combination of Liaw and Lee does not disclose “edge cells surrounding the logic block”.
In a similar art, Chiu discloses an integrated circuit structure (100) with edge cells (edge cell straps 108, 112) surrounding the logic block (SRAM array 102), FIG. 1 reproduced below, [0029].
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Chiu: FIG. 1
Chiu discloses that a semiconductor device as taught enhances circuit performance and reliability [0002]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Liaw and Lee’s device, in order to enhance circuit performance and reliability as disclosed by Chiu [0002].
Regarding Claim 11, The combination of Liaw, Lee, and Chiu discloses the semiconductor device according to claim 10.
Liaw discloses: further comprising: each backside metal Vdd power rail (Liaw: 622 Vdd) of the set of backside metal Vdd power rails is continuous (Liaw: FIG. 6B, [0076]); and
each backside metal Vss power rail (Liaw: 622 Vss) of the set of backside metal Vss power rails is continuous, FIG. 6B, [0076].
Liaw [0076] discloses the conductive routing lines 622 vdd and 622 vss are backside conductive routing lines connected to high-voltage source VDD and low-voltage source VSS respectively; and FIG. 6B shows them as continuous rails across the logic block, indicating the backside metal Vdd power rail and the frontside metal Vdd power rails are continuous with no breaks across the logic block.
Liaw does not disclose “the Vdd and Vss power rails with a break only surrounding the first macro cell.”
In a similar art, Lee discloses a semiconductor device with plurality of integrated circuits 20, wiring structure 30, and a plurality of TSV structures 40, FIG. 1A, [0025].
Lee [0052] discloses that the semiconductor device includes power wiring layers VDD and VSS that supply power to the integrated circuit. Lee FIG.10, [0076] discloses an operation D130 where hard macro is disposed in the semiconductor device. After that, in operation D140 logic cells are placed in the integrated circuit area such that logic cells do not overlap the hard macro. Further, in operation D150 hard macros and the logic cells are electrically connected for routing. Since the hard macros are placed such that the logic cells do not overlap the macro, routing structures including the power lines are arranged around the macro region, indicating the power rails are continuous with a break surrounding the macro cell.
Lee discloses that a device as taught improves routing efficiency and increases communication speed of the semiconductor device [0080]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the device in order to increase communication speed as disclosed by Lee [0080].
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Liaw in view of Xie, further in view of Chiu.
Regarding Claim 18, Liaw discloses a method comprising:
forming a logic block (40), wherein the logic block comprises circuitry for one logic function of a semiconductor device, FIG. 1, [0021], [0022].
wherein the logic block (40) comprises a set of circuit rows (memory cell array 402, FIG. 4, [0057]), a set of backside metal Vdd power rails (622 vdd, FIG. 6B, [0076]), a set of backside metal Vss power rails (622 vss, FIG. 6B, [0076]);
forming a frontside to backside signal via (430, FIG. 5E) vertically aligned and directly connecting a first backside metal signal (222wl, [0053]) to a first frontside metal signal (426, [0060]),
wherein the frontside to backside signal via (430) is within the first edge cells (422c), FIG. 5E, [0065].
Liaw discloses a first nanosheet transistor device 628a and second nanosheet transistor 628b, FIG. 6C, [0070]. Liaw does not disclose “forming a double diffusion break region between a first nanosheet transistor device and a second nanosheet transistor device of the logic block, wherein a first gate structure of the first nanosheet transistor device wraps around ends of first channel nanosheets in the double diffusion break region, and a second gate structure of the second nanosheet transistor device wraps around ends of second channel nanosheets in the double diffusion break region.”
In a similar art, Xie discloses IC structures incorporating isolation and diffusion break elements [col.1, line 11].
Xie discloses: a double diffusion break region (194, FIG. 4, [col.9, line7]) arranged between a first nanosheet transistor device (nanosheet stack 200) and a second nanosheet transistor device (nanosheet stack 200) of the logic block (set of logic transistors in structure 100, FIG. 4, [col. 16, line 33]).
wherein a first gate structure (162) of the first nanosheet transistor device (200) wraps around ends of first channel nanosheets (210) in the double diffusion break region (194), FIG. 5, [col. 9, line 3, line 60].
and a second gate structure (162) of the second nanosheet transistor device (200) wraps around ends of second channel nanosheets (210) in the double diffusion break region (194), FIG. 5, [col. 9, line 3, line 60];
Xie (FIG. 5, [col. 9, line 60]) discloses nanosheet stacks 200 includes a plurality of semiconductor nanosheets 210 alternating with portions of gate region 162 filling space between each semiconductor nanosheet 210, indicating the gate structure wraps around ends of each channel nanosheet 210.
Xie [col. 9, line 3] discloses the diffusion break region 194 may horizontally separate a pair of upper surfaces U1, U2 of isolation layer 192 from each other, with each upper surface U1, U2 corresponding to one active layer 110A, 110B. Xie (FIG.4, [col. 9, line 14]) discloses diffusion break region 194 may extend upward from isolation layer 192 and may be integral with isolation layer 192, indicating the gate structures of the nanosheet transistor devices which wraps around ends of channel nanosheets 210 are located in the double diffusion break region 194.
The combination of Liaw and Xie discloses: wherein the frontside to backside signal via (Liaw: 430, FIG. 5E, [0065]) passes through the double diffusion break region directly between the first gate structure and the second gate structure (Xie: double diffusion break region 194 between first gate structure 162 and second gate structure 162, FIG. 4, [col. 9, line 3, line 60]).
Xie discloses that a device as taught mitigates parasitic current leakage and improves performance [col. 1, line 25]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Liaw’s device in order to mitigate parasitic current leakage and improve performance as disclosed by Xie [col. 1, line 25].
The combination of Liaw and Xie does not disclose “first edge cells arranged along a perimeter of the logic block.”
In a similar art, Chiu discloses an integrated circuit structure (100) with first edge cells (edge cell straps 108, 112) arranged along a perimeter of the logic block (SRAM array 102), FIG. 1, [0029].
Chiu discloses that a semiconductor device as taught enhances circuit performance and reliability [0002]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Liaw and Xie’s device, in order to enhance circuit performance and reliability as disclosed by Chiu [0002].
Claims 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Liaw in view of Xie, further in view of Chiu, still further in view of Lee.
Regarding Claim 19, The combination of Liaw, Xie, and Chiu disclose the method according to claim 18.
Liaw discloses: forming a second frontside to backside signal via (430, [0065]) vertically aligned and directly connecting a second backside metal signal (222 wl, [0053]) to a second frontside metal signal (426, [0060]), FIG. 5E.
wherein the second frontside to backside signal via (430) is only within one of the second edge cells (422c), FIG. 5E, [0065].
Liaw discloses each edge cells 422 may include a word line tap structure 424, thereby a second frontside to backside signal via 430 is vertically aligned and directly connects a second backside metal signal to a second frontside metal signal.
The combination of Liaw, Xie, and Chiu does not disclose “forming a macro cell within the logic block, wherein the macro cell comprises second edge cells arranged along a perimeter of the macro cell, wherein both the macro cell and the second edge cells are within the perimeter of the logic block.”
In a similar art, Lee discloses a semiconductor device 100A with plurality of integrated circuits 20, wiring structure 30, and a plurality of TSV structures 40, FIG. 1A, [0025].
Lee discloses an operation (D130) of disposing a hard macro or a hard block in the first integrated circuit area and the second integrated circuit area of each of the semiconductor devices (e.g., stack 1, stack 2, . . . stack N), FIG. 10, [0076].
Lee discloses: forming a macro cell (hard macro) within the logic block (first integrated circuit 20-1), FIG. 10, [0076].
Chiu discloses an integrated circuit structure (100) with edge cells (edge cell straps 108, 112) surrounding the logic block (SRAM array 102), FIG. 1, [0029].
The combination of Lee and Chiu disclose: wherein the macro cell (Lee: hard macro) comprises second edge cells (Chiu: edge cell straps 108, 112) arranged along a perimeter of the macro cell (Lee: hard macro), wherein both the macro cell (Lee: hard macro) and the second edge cells are within the perimeter of the logic block (Chiu: edge cells straps 108, 112 surrounding the logic block (SRAM array 102, FIG. 1, [0029]).
Lee discloses that a device as taught increases communication speed of the semiconductor device [0080]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Liaw, Xie, and Chiu’s device in order to increase communication speed as disclosed by Lee [0080].
Regarding Claim 20 (Currently Amended), The combination of Liaw, Xie, Chiu, and Lee disclose the method according to claim 19.
Liaw discloses a logic block (400) comprises a set of circuit rows (memory cell array 402 has m rows by n columns for bit cells 102, FIG. 4, [0057]),
Lee discloses forming a macro cell (hard macro) within the logic block (first integrated circuit 20-1), FIG. 10, [0077].
The combination of Liaw and Lee discloses: wherein the logic block comprises a set of circuit rows (Liaw: memory circuit 400 includes a memory cell array 402, FIG. 4, [0057]), wherein at least one circuit row of the set of circuit rows is interrupted by the macro cell (Lee: hard macro, FIG. 10, [0077]).
Lee FIG.10 discloses an operation D130 where hard macro is disposed in the semiconductor device. After that in operation D140 logic cells are placed in the integrated circuit area such that logic cells do not overlap the hard macro. Further in operation D150 hard macros and the logic cells are electrically connected for routing, thereby the hard macros are placed in a manner the row of logic cells are interrupted.
Lee discloses that a device as taught improves routing efficiency and increases communication speed of the semiconductor device [0080]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Liaw, Xie, and Chiu’s device in order to increase communication speed as disclosed by Lee [0080].
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Liaw in view of Lee, further in view Chiu, still further in view of Cheng et al. (US20120206953A1; hereinafter Cheng).
Regarding Claim 13 (Currently Amended), The combination of Liaw, Lee, and Chiu discloses the semiconductor device according to claim 10.
Liaw discloses: further comprising: a third frontside to backside signal via (730) vertically aligned and directly connecting a first backside metal Vdd power rail (622 Vdd) of the set of backside metal Vdd power rails to a front side Vdd power rail (218 Vdd) of the set of front side Vdd power rails, FIG. 7, [0080].
The combination of Liaw, Lee, and Chiu does not disclose “wherein the third frontside to backside signal via is only in a top edge cell of the logic block.”
In a similar art, Cheng discloses a memory device with edge cells [0001].
The combination of Liaw and Cheng discloses: further comprising: wherein the third frontside to backside signal via (Liaw: 730, [0080]) is only in a top edge cell of the logic block (Cheng: FIG. 1, [0022]).
Liaw [0057] discloses the strap cells 418 positioned on the top and bottom of the array are configured to supply bulk terminal voltages; and Liaw [0078] discloses the power conductor strap structures 724 including the third frontside to backside signal via 730 are positioned in a suitable place in the integrated circuit, indicating the via 730 can be placed in the strap cells. Cheng [0022] discloses the placement of power management edge cells only on the top of the SRAM cell array in SEG-1, indicating third frontside to backside signal via can be placed only in a top edge cell of the logic block.
Cheng discloses that a device as taught enhances performance of the memory device [0023]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Liaw, Lee, and Chiu’s device, in order to enhance performance as disclosed by Cheng [0023].
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/Krishna J Palaniswamy/
Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899