DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-11 in the reply filed on 11/20/2025 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 8 & 10 are rejected under 35 U.S.C. 102(a)(1) and/or 102(a)(2) as being anticipated by Poddar et al. (US Pub. 2023/0005881).
Regarding claim 1, Poddar teaches a semiconductor device, comprising:
a substrate 329 (Fig. 3C & Fig. 7);
a first semiconductor structure on the substrate 329 (see Fig. 3C below);
a second semiconductor structure on the first semiconductor structure (Fig. 3C below); and
a wire 325 coupled between the substrate 329 and the first semiconductor structure, wherein the first semiconductor structure and the second semiconductor structure are electrically connected to the substrate 329 through the wire 325 (Fig. 3C below),
wherein a footprint of the first semiconductor structure is greater than a footprint of the second semiconductor structure (Fig. 3C & Fig. 7).
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Regarding claim 2, Poddar teaches the semiconductor device according to claim 1, wherein the first semiconductor structure comprises:
a first semiconductor layer 203 (a semiconductor die are understood to have semiconductor layer/s);
a first conductive structure on the first semiconductor layer (see Fig. 3C above); and
a first bonding pad on the first conductive structure and electrically connected to the first conductive structure (see Fig. 3C above),
wherein the second semiconductor structure comprises:
a second semiconductor layer 301; (a semiconductor die are understood to have semiconductor layer/s)
a second conductive structure 421 on the second semiconductor layer (Fig. 3C, also see Fig. 4C); and
a second bonding pad 425 on the second conductive structure 421 and electrically connected to the second conductive structure 421 (Fig. 3C, also see Fig. 4C),
wherein the first conductive structure, the first bonding pad, the second conductive structure 421 and the second bonding pad 425 are between the first semiconductor layer 203 and the second semiconductor layer 301 (Fig. 3C).
Regarding claim 3, Poddar teaches the semiconductor device according to claim 2, wherein the first bonding pad of the first semiconductor structure is bonded to the second bonding pad of the second semiconductor structure (see Fig. 3C).
Regarding claim 8, Poddar teaches the semiconductor device according to claim 1, wherein the first semiconductor structure is bonded to the second semiconductor structure in a face-to-face bonding arrangement (Fig. 3C and respective text).
Regarding claim 10, Poddar teaches the semiconductor device according to claim 1, wherein the first semiconductor structure is a memory chip, and the second semiconductor structure is a memory chip (Fig. 3C, both first and second semiconductor structure can function as memory chips). Furthermore, it has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex Parte Masham, 2 USPQ F.2d 1647 (1987).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-7, 9 & 11 are rejected under 35 U.S.C. 103 as being unpatentable over Poddar as applied to claim 1 above, and in further view of WEI et al. (US Pub. 2022/0367391).
Regarding claim 8, Poddar is silent on the semiconductor device according to claim 2, wherein the first semiconductor structure comprises an oxide film on the first bonding pad and a conductive portion in the oxide film, the conductive portion is between the first bonding pad of the first semiconductor structure and the second bonding pad of the second semiconductor structure.
However, WEI discloses wherein a first semiconductor structure 600 comprises an oxide film (e.g. 208) on a first bonding pad 204 and a conductive portion 216 in the oxide film 208, the conductive portion 216 is between the first bonding pad 204 of the first semiconductor structure 600 and a second bonding pad 104 of a second semiconductor structure 500 (see Fig. 5D). This has the advantage of providing an improved and mechanically stable bonding structure between the two semiconductor structures. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Poddar with the bonding structure, as taught by WEI, so as to obtain a semiconductor device with improved bonding/contact structure.
Regarding claims 5-6, the combination of Poddar and WEI teaches the semiconductor device according to claim 4, wherein the conductive portion comprises Ti, TiN, Ta, TaN, Co, Mo, Cr, Mn or Si (claim 5); and wherein the conductive portion comprises MCu, M comprises Ti, TiN, Ta, TaN, Co, Mo, Cr, Mn or Si (see Para [0075, wherein WEI teaches said claim material for the various components of the interconnect structure).
Regarding claim 7, the combination of Poddar and WEI teaches the semiconductor device according to claim 4, wherein the oxide film 208 comprises MSiOx, M comprises Ti, TiN, Ta, TaN, Co, Mo, Cr, Mn or Si, and x is greater than zero (208 is SiOx, where x is greater than zero, and it is understood that at the interface of SiOx layer 208 and Ti/Ta/Cr/Mn conductive portion 116, there is an inherent MSiOx layer).
Regarding claim 9, Poddar is silent on the semiconductor device according to claim 8, wherein the first semiconductor structure comprises an oxide film on the first bonding pad and a conductive portion in the oxide film, the conductive portion comprises Ti or TiCu. However, WEI teaches in Fig. 5D wherein a first semiconductor structure 600 comprises an oxide film 216 on a first bonding pad 204 and a conductive portion 216 in the oxide film 216, the conductive portion comprises Ti or TiCu (Para [0075]). This has the advantage of providing an improved and mechanically stable bonding structure between the two semiconductor structures. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Poddar with the bonding structure, as taught by WEI, so as to obtain a semiconductor device with improved bonding/contact structure.
Regarding claim 11, Poddar teaches a semiconductor device, comprising:
a first semiconductor structure having a first active surface (see Fig. 3C above); and
a second semiconductor structure having a second active surface (see Fig. 3C above), wherein the second active surface of the second semiconductor structure faces toward the first active surface of the first semiconductor structure (Para [0028], and the first semiconductor structure is bonded to the second semiconductor structure (Fig. 3C).
Poddar is silent on wherein the first active surface of the first semiconductor structure comprises Ti (Poddar teaches wherein the first active surface comprises Cu). However, WEI teaches in Para [0075] and Fig. 5D a semiconductor structure 600 comprising a first active surface comprising metallic interconnect that list Ti and Cu among the known material. Before the effective filing date of the claim invention, one of the ordinary skill in the art would have pursued such known options within his/her technical grasp by replacing Cu with Ti with reasonable expectation of success. As such, said claim feature would have been obvious and within the ordinary skill in the art.
Conclusion
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/TIMOR KARIMY/Primary Examiner, Art Unit 2818