DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Un-der37CFR 1.114
2. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02/13/2026 has been entered.
Claim Rejections - 35 USC § 102
3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
4. Claim(s) 1-5, 7, 9, is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al., US 2018/0294241 A1.
Claim 1. Chen et al., disclose a semiconductor package (such as the one in fig. 20) comprising:
-a first package level including one or more first-level chip-lets (item 100, fig. 12, 20);
-a second package level including one or more second-level chip-lets (item 68A/68B, fig. 12, 20);
-wherein the first package level is hybrid bonded with the second package level (this limitation would read through [0035] wherein is disclosed that the bonding may be achieved through hybrid bonding);
-a heat spreader (item 88/94, [0042]) bonded to the second package level with a metallic layer including a layer of one or more intermetallic compounds (item 92/86);
-and straight package sidewalls spanning and formed of the second package level, the metallic layer, and the metallic layer heat spreader (as seen in the structure of fig. 20, wherein all items are coplanar on the side-wall, for example [0050] recites a die-saw step is performed on composite wafer 102 to separate composite wafer 102 into a plurality of packages 104).
Claim 2. Chen et al., disclose the semiconductor package of claim 1, wherein the one or more first-level chip-lets are hybrid bonded to the second package level (this limitation would read through [0035] wherein is disclosed that the bonding may be achieved through hybrid bonding).
Claims 3-5. Chen et al., disclose the semiconductor package of claim 2, further comprising a plurality of metal pillars (item 110, fig. 20, [0050]) extending away from the second package level and laterally adjacent to the one or more first-level chip-lets.
Claims 7, 9. Chen et al., disclose the semiconductor package of claim 1, wherein: the one or more first-level chip-lets are oxide-oxide bonded to a common insulator layer of the second package level; the one or more first-level chip-lets are embedded in a first gap fill material; and the one or more second-level chip-lets are embedded in a second gap fill material; and wherein the straight package sidewalls span the first gap fill material, the common insulator layer, and the second gap fill material (this limitation would read through [0038] wherein is disclosed that in accordance with alternative embodiments of the present disclosure in which gap-filling material 80 is formed of an oxide (such as silicon oxide), a thin layer of gap-filling material 80 may be left over substrates 70A and 70B).
Allowable Subject Matter
5. Claims 11-20 are allowed.
Reasons for Allowance
6. The following is an examiner's statement of reasons for allowance:
7. Regarding claims 11-12, the prior art failed to disclose or reasonably suggest over-molding the second-level chip-lets with a gap fill material to form a second package level; bonding a heat spreader to the second package level with a metallic layer using transient liquid phase bonding; and singulating a plurality of semiconductor packages, each semiconductor package of the plurality of semiconductor packages including straight package sidewalls spanning and formed of the second package level, the metallic layer, and the heat spreader.
8. Regarding claims 13-17, the prior art failed to disclose or reasonably suggest exposing back sides of the plurality of second-level chip-lets; bonding a heat spreader to the gap fill material and the back sides of the plurality of second-level chip-lets with a metallic layer using transient liquid phase bonding; and removing the carrier substrate; hybrid bonding one or more first-level chip-lets to the second package level of the second reconstituted wafer; and singulating a plurality of semiconductor packages, each semiconductor package of the plurality of semiconductor packages including straight package sidewalls spanning and formed of the second package level, the metallic layer, and the heat spreader.
9. Regarding claims 18-20, the prior art failed to disclose or reasonably suggest wherein the second reconstituted wafer includes: the second package level including a plurality of second-level chip-lets encapsulated in a gap fill material; and a heat spreader bonded to back sides of the plurality of second-level chip-lets with a metallic layer including a layer of one or more intermetallic compounds; wherein the first package level includes one or more first-level chip-lets; and singulating a plurality of semiconductor packages, each semiconductor package of the plurality of semiconductor packages including straight package sidewalls spanning and formed of the first package level, second package level, the metallic layer, and the heat spreader.
Response to Arguments
10. Applicant's arguments filed 02/13/2026 have been fully considered but they are not persuasive.
Applicant first avers with respect to claim 1, that Chen et al., fails to teach, disclose, or suggest all features recited by previously presented independent claim 1. As amended the independent claim 1 recites, inter alia: "straight package sidewalls spanning and formed of the second package level, the metallic layer, and the metallic layer heat spreader".
In response:
a) It is noted that [0050], fig. 20 of Chen’s reference clearly states, for example “a die-saw step is performed on composite wafer 102 to separate composite wafer 102 into a plurality of packages 104”.
b) As by definition, the die-saw step in semiconductor packaging refers to the process of separating a finished wafer into individual dies or chips, which are then encapsulated into chip carriers suitable for electronic devices. This process is crucial for the assembly of integrated circuits (ICs) and other semiconductor devices. The die-saw step is typically automated to ensure precision and accuracy, and it can involve various methods such as mechanical sawing, laser cutting, or scribing and breaking. The resulting individual silicon chips are then packaged in suitable carriers or placed directly on printed circuit boards for use in electronic devices (see Wikipedia).
c) It is also noted that the reference provides a structure similar such as the one in fig. 20 of Chen et al., with respect to applicant’s fig. 1. It is evidence that ordinary workers skilled in the art would find reasons, suggestions or motivations to use the straight package sidewalls spanning and formed of the second package level, the metallic layer, and the metallic layer heat spreader in the claim would in the structure of fig. 20, wherein all items are coplanar on the side-wall, for example [0050] recites a die-saw step is performed on composite wafer 102 to separate composite wafer 102 into a plurality of packages 104). As noted, labels, statements of intended use, or functional language do not structurally distinguish claims over prior art. The structure of the device is substantially identical to that of the claimed structure which can function in the same manner, be labeled in the same manner, or be used in the same manner. MPEP 2112.01.
Thus, Examiner believe that the present claim language of the limitation claimed would not place the application in condition for allowance.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILNER JEAN BAPTISTE whose telephone number is (571)270-7394. The examiner can normally be reached M-T 8:00-6:00.
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/W.J/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899