DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office action is in response to the amendment filed 4/10/2026 in which claims 14 and 19 were amended.
Claims 1-20 are pending with claims 1, 2, 6, 7, 9-12, and 14-19 presented for examination and claims 3-5, 8, 13, and 20 remaining withdrawn.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 6, 7, 9-12, 14, and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hoshi (US 2020/0373292 and Hoshi hereinafter).
As to claims 1, 2, 6, 7, 9-12, 14, and 16: Hoshi discloses [claim 1] a semiconductor device (Figs. 2 and 4; 20; [0074]), comprising: an n-type semiconductor substrate (31; [0078]); a drift layer (32; [0078]), wherein the drift layer (32) is disposed on a surface (top surface) of the n-type semiconductor substrate (31); a semiconductor layer (portion of 34a not in direction contact with 35a, 36a, and 62a; [0078]), wherein the semiconductor layer (portion of 34a not in direction contact with 35a, 36a, and 62a) is disposed on a surface (top surface) that is of the drift layer (32) and that is away from the n-type semiconductor substrate (31), and wherein the semiconductor layer (portion of 34a not in direction contact with 35a, 36a, and 62a) comprises a source region (35a; [0078]), the source region (35a) is an n-type semiconductor region (n+; [0078]), and the source region (35a) is exposed on a side (top surface) that is of the semiconductor layer (portion of 34a not in direction contact with 35a, 36a, and 62a) and that is away from the drift layer (32); a groove (37a; [0080]), wherein an opening of the groove (37a) is located on a surface that is of the semiconductor layer (portion of 34a not in direction contact with 35a, 36a, and 62a) and that is away from the drift layer (32), a gate (39a; [0080]) is disposed in the groove (37a), and a gate oxide layer (38a is an oxide; [0080] and [0138]) is disposed between the gate (39a) and a surface (sidewall) of the groove (37a); a p-type shielding structure (comprising 62a and 90a; [0083] and [0109]), wherein the p-type shielding structure (comprising 62a and 90a) is disposed at the drift layer (32), the p-type shielding structure (comprising 62a and 90a) comprises a plurality of first shielding structures (62a) and a plurality of second shielding structures (90a), each of the plurality of first shielding structures extends in a first direction (X-direction; [0083]), each of the plurality of second shielding structures (90a) extends in a second direction (Y-direction; [0109]), the first direction (X-direction) intersects with the second direction (Y-direction), and the plurality of first shielding structures (62a) and the plurality of second shielding structures (90a) are disposed in a grid shape (as shown in Fig. 4); a source (comprising 41a, 46a, and 21a; [0086]-[0091]) disposed on the side (top surface) that is of the semiconductor layer (portion of 34a not in direction contact with 35a, 36a, and 62a) and that is away from the drift layer (32), wherein the source (comprising 41a, 46a, and 21a) is in contact with the source region (41a is in contact with 35a) and a gate insulation layer (40 is the gate insulation layer, 42a is in contact with 40; [0085]); and a drain (51; [0094]) disposed on a side (bottom surface) that is of the n-type semiconductor substrate (31) and that is away from the drift layer (32); [claim 2] wherein: each of the plurality of first shielding structures (62a) is bar-shaped (as shown in Fig. 4), and the plurality of first shielding structures (62a) are parallel to each other and arranged at spacings of a first specified distance (as shown in Fig. 4); and each of the plurality of second shielding structures (90a) is bar-shaped (as shown in Fig. 4), and the plurality of second shielding structures (90a) are parallel to each other and arranged at spacings of a second specified distance (as shown in Fig. 4); [claim 6] wherein the first direction (X-direction) is perpendicular to the second direction (Y-direction); [claim 7] wherein the p-type shielding structure (comprising 62a and 90a) extends in a fifth direction (Z-direction), and the fifth direction (Z-direction) is perpendicular to the first direction (X-direction) and the second direction (Y-direction); [claim 9] further comprising a first semiconductor region (36a; [0078]) and a well region (portion of 34a that is in direct contact with 35a, 36a, and 62a) that are located at the semiconductor layer (portion of 34a not in direction contact with 35a, 36a, and 62a), wherein: the first semiconductor region (36a) is a p-type semiconductor region (p++; [0078]), and the well region (portion of 34a that is in direct contact with 35a, 36a, and 62a) is a p-type semiconductor region (p; [0078]); the well region (portion of 34a that is in direct contact with 35a, 36a, and 62a) is in contact with the p-type shielding structure (comprising 62a and 90a), the source region (35a), and the first semiconductor region (36a), and the first semiconductor region (36a) is further in contact with the source (41a is in contact with 36a); and a doping concentration of the first semiconductor region (36a is p++) is greater than a doping concentration of the p-type shielding structure (62a is p+); [claim 10] wherein an orthographic projection of the first semiconductor region (36a) on the n-type semiconductor substrate (31) coincides with an orthographic projection of an overlapping region (area adjacent to 33a that overlaps with 36a that is to the right of rightmost 37a in Fig. 2 when also viewing the right side of Fig. 4 for the plan view) between a respective first shielding structure (62a) and a respective second shielding structure (90a) on the n-type semiconductor substrate (31); [claim 11] wherein an orthographic projection of the first semiconductor region (36a) on the n-type semiconductor substrate (31) coincides with (36a and 62a overlap in the Z-direction) an orthographic projection of the p-type shielding structure (comprising 62a and 90a) on the n-type semiconductor substrate (31); [claim 12] wherein a doping concentration of the well region (34a is p) is less than the doping concentration of the first semiconductor region (36a is p++); [claim 14] wherein a distance between the n-type semiconductor substrate (top of 31) and a surface (bottom of 62a) that is of the p-type shielding structure (comprising 62a and 90a) and that faces the n-type semiconductor substrate (31) is less than a distance between the n-type semiconductor substrate (top of 31) and a surface (bottom of 37a) that is of the groove and that faces the n-type semiconductor substrate (31); [claim 16] wherein the p-type shielding structure (comprising 62a and 90a) is symmetrically disposed (62a is disposed symmetrically on both sides of rightmost 37a as shown in Fig. 2) on a peripheral side of the groove (37a).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Hoshi in view of Iwahashi et al (US 2023/0143618 and Iwahashi hereinafter).
Although the structure disclosed by Hoshi shows substantial features of the claimed invention (discussed in paragraph 6 above), it fails to expressly disclose:
wherein a distance between the n-type semiconductor substrate and a surface that is of a respective first shielding structure and that faces the n-type semiconductor substrate is different from a distance between the n-type semiconductor substrate and a surface that is of a respective second shielding structure and that faces the n-type semiconductor substrate.
Hoshi discloses first shielding structures 62a and second shielding structures 90a that intersect with one another in Fig. 4 for a vertical transistor.
Iwahashi discloses in Fig. 1 a vertical transistor wherein a distance between the n-type semiconductor substrate (11; [0030]) and a surface (bottom surface) that is of a respective first shielding structure (18; [0036]) and that faces the n-type semiconductor substrate (11) is different from a distance between the n-type semiconductor substrate (11) and a surface (bottom surface) that is of a respective second shielding structure (15; [0033]) and that faces the n-type semiconductor substrate (11).
Given the teachings of Iwahashi, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Hoshi by employing the well-known or conventional features of vertical MOSFET fabrication, such as displayed by Iwahashi, by employing second shielding structures that form a grid with first shielding structures and where the distances between respective first and second shielding structures bottom surfaces and the top surface of the semiconductor substrate are different in order to suppress breakage of the gate oxide layer while suppressing the decrease in breakdown voltage ([0073]).
Claims 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Hoshi (US 2022/0157778 and Hoshi2 hereinafter) in view of Hoshi.
As to claim 17: Hoshi2 discloses an integrated circuit (Figs. 5, 6, and 9; 100; [0055]), comprising a circuit board (90; [0083]) and a semiconductor device (20; [0055]) disposed on the circuit board (90), wherein the semiconductor device comprises: an n-type semiconductor substrate (31; [0071]); a drift layer (32; [0071]), wherein the drift layer (32) is disposed on a surface (top surface) of the n-type semiconductor substrate (31); a semiconductor layer (portion of 34a not in direction contact with 35a, 36a, and 62a; [0071]), wherein the semiconductor layer (portion of 34a not in direction contact with 35a, 36a, and 62a) is disposed on a surface (top surface) that is of the drift layer (32) and that is away from the n-type semiconductor substrate (31), and wherein the semiconductor layer (portion of 34a not in direction contact with 35a, 36a, and 62a) comprises a source region (35a; [0071]), the source region (35a) is an n-type semiconductor region (n+; [0071]), and the source region (35a) is exposed on a side (top surface) that is of the semiconductor layer (portion of 34a not in direction contact with 35a, 36a, and 62a) and that is away from the drift layer (32); a groove (37a; [0072]), wherein an opening of the groove (37a) is located on a surface that is of the semiconductor layer (portion of 34a not in direction contact with 35a, 36a, and 62a) and that is away from the drift layer (32), a gate (39a; [0073]) is disposed in the groove (37a), and a gate oxide layer (38a is an oxide; [0073] and [0143]) is disposed between the gate (39a) and a surface (sidewall) of the groove (37a); a p-type shielding structure (62a; [0076]), wherein the p-type shielding structure (62a) is disposed at the drift layer (32), the p-type shielding structure (62a) comprises a plurality of first shielding structures (62a); a source (comprising 41a, 46a, and 21a; [0078]-[0082]) disposed on the side (top surface) that is of the semiconductor layer (portion of 34a not in direction contact with 35a, 36a, and 62a) and that is away from the drift layer (32), wherein the source (comprising 41a, 46a, and 21a) is in contact with the source region (41a is in contact with 35a) and a gate insulation layer (40 is the gate insulation layer, 42a is in contact with 40; [0066]); and a drain (51; [0085]) disposed on a side (bottom surface) that is of the n-type semiconductor substrate (31) and that is away from the drift layer (32).
Hoshi2 fails to expressly disclose where the p-type shielding structure comprises a plurality of second shielding structures, each of the plurality of first shielding structures extends in a first direction, each of the plurality of second shielding structures extends in a second direction, the first direction intersects with the second direction, and the plurality of first shielding structures and the plurality of second shielding structures are disposed in a grid shape.
Hoshi discloses a plurality of second shielding structures (Figs. 2 and 4; 90a; [0109]), each of the plurality of first shielding structures extends (62a; [0073]) in a first direction (X-direction; [0083]), each of the plurality of second shielding structures (90a) extends in a second direction (Y-direction; [0109]), the first direction (X-direction) intersects with the second direction (Y-direction), and the plurality of first shielding structures (62a) and the plurality of second shielding structures (90a) are disposed in a grid shape (as shown in Fig. 4).
Given the teachings of Hoshi, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Hoshi2 by employing the well-known or conventional features of vertical MOSFET fabrication, such as displayed by Hoshi, by employing second shielding structures that form a grid with first shielding structures in order to improve the reverse recovery resistance of the device ([0122]).
As to claims 18 and 19: Hoshi2 discloses [claim 18] an electronic device (Figs. 5, 6, and 9; 100; [0055]), comprising a housing (89; [0100]) and an integrated circuit (comprising 10 and 90; [0100]-[0101]) disposed in the housing (89), wherein the integrated circuit (comprising 10 and 90) comprises a circuit board (90; [0083]) and a semiconductor device (20; [0055]) disposed on the circuit board (90), and wherein the semiconductor device comprises: an n-type semiconductor substrate (31; [0071]); a drift layer (32; [0071]), wherein the drift layer (32) is disposed on a surface (top surface) of the n-type semiconductor substrate (31); a semiconductor layer (portion of 34a not in direction contact with 35a, 36a, and 62a; [0071]), wherein the semiconductor layer (portion of 34a not in direction contact with 35a, 36a, and 62a) is disposed on a surface (top surface) that is of the drift layer (32) and that is away from the n-type semiconductor substrate (31), and wherein the semiconductor layer (portion of 34a not in direction contact with 35a, 36a, and 62a) comprises a source region (35a; [0071]), the source region (35a) is an n-type semiconductor region (n+; [0071]), and the source region (35a) is exposed on a side (top surface) that is of the semiconductor layer (portion of 34a not in direction contact with 35a, 36a, and 62a) and that is away from the drift layer (32); a groove (37a; [0072]), wherein an opening of the groove (37a) is located on a surface that is of the semiconductor layer (portion of 34a not in direction contact with 35a, 36a, and 62a) and that is away from the drift layer (32), a gate (39a; [0073]) is disposed in the groove (37a), and a gate oxide layer (38a is an oxide; [0073] and [0143]) is disposed between the gate (39a) and a surface (sidewall) of the groove (37a); a p-type shielding structure (62a; [0076]), wherein the p-type shielding structure (62a) is disposed at the drift layer (32), the p-type shielding structure (62a) comprises a plurality of first shielding structures (62a); a source (comprising 41a, 46a, and 21a; [0078]-[0082]) disposed on the side (top surface) that is of the semiconductor layer (portion of 34a not in direction contact with 35a, 36a, and 62a) and that is away from the drift layer (32), wherein the source (comprising 41a, 46a, and 21a) is in contact with the source region (41a is in contact with 35a) and a gate insulation layer (40 is the gate insulation layer, 42a is in contact with 40; [0066]); and a drain (51; [0085]) disposed on a side (bottom surface) that is of the n-type semiconductor substrate (31) and that is away from the drift layer (32).
Hoshi2 fails to expressly disclose where the p-type shielding structure comprises [claim 18] a plurality of second shielding structures, each of the plurality of first shielding structures extends in a first direction, each of the plurality of second shielding structures extends in a second direction, the first direction intersects with the second direction, and the plurality of first shielding structures and the plurality of second shielding structures are disposed in a grid shape; [claim 19] wherein: each first shielding structure is bar-shaped, and the plurality of first shielding structures are parallel to each other and arranged at spacings of a first specified distance; and each second shielding structure is bar-shaped, and the plurality of second shielding structures are parallel to each other and arranged at spacings of a second specified distance.
Hoshi discloses [claim 18] a plurality of second shielding structures (Figs. 2 and 4; 90a; [0109]), each of the plurality of first shielding structures extends (62a; [0073]) in a first direction (X-direction; [0083]), each of the plurality of second shielding structures (90a) extends in a second direction (Y-direction; [0109]), the first direction (X-direction) intersects with the second direction (Y-direction), and the plurality of first shielding structures (62a) and the plurality of second shielding structures (90a) are disposed in a grid shape (as shown in Fig. 4); [claim 19] wherein: each first shielding structure (62a) is bar-shaped (as shown in Fig. 4), and the plurality of first shielding structures (62a) are parallel to each other and arranged at spacings of a first specified distance (as shown in Fig. 4); and each second shielding structure (90a) is bar-shaped (as shown in Fig. 4), and the plurality of second shielding structures (90a) are parallel to each other and arranged at spacings of a second specified distance (as shown in Fig. 4).
Given the teachings of Hoshi, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Hoshi2 by employing the well-known or conventional features of vertical MOSFET fabrication, such as displayed by Hoshi, by employing second shielding structures that form a grid with first shielding structures, where the shielding structures are bar-shaped and respectively spaced apart, in order to improve the reverse recovery resistance of the device ([0122]).
Response to Arguments
Applicant’s arguments, see page 9, lines 1-3, filed 4/10/2026, with respect to the 35 USC 112(b) rejection of claims 1, 17, and 18 have been fully considered and are persuasive. The rejection of 2/13/2026 has been withdrawn.
Applicant's arguments filed 4/10/2026 have been fully considered but they are not persuasive.
In the remarks, applicant argues in substance that Hoshi does not disclose both a gate oxide layer and a gate insulation layer.
Examiner respectfully traverses applicant’s remarks. Hoshi and Hoshi2 disclose in Fig 2 or Fig. 4, respectively, an insulating layer 40 that is over the gate (although this feature isn’t claimed, it is consistent with the instant specification) and in contact with the source, specifically 42a in 46a, that is interpreted to be the gate insulation layer. Therefore, Hoshi and Hoshi2 disclose both a gate oxide layer 38a and a gate insulation layer 40.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH C NICELY whose telephone number is (571)270-3834. The examiner can normally be reached Monday-Friday 7:30 am - 4 pm, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached at (571) 270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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JOSEPH C. NICELY
Primary Examiner
Art Unit 2813
/JOSEPH C. NICELY/Primary Examiner, Art Unit 2813
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