DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-9 and 13 have been considered but are moot on grounds of new rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-9 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sato et al. (Sato) (JP 2021027241 A) as evidenced by or in view of Taniguchi et al. (Taniguchi) (JP 200931690 A) or Inumiya et al. (Inumiya) (JP 2019169579 A) in view of Niimi (JP 2010103350 A1).
In regards to claim 1, Sato (Figs. 2, 3, 5 and associated text) discloses a semiconductor device, comprising: a base member (item 16) including a first surface (item 16b, bottom surface of item 16), a second surface (item 16a, upper surface of item 16), and a protrusion (item A1), the second surface (item 16a, upper surface of item 16) being at a side opposite to the first surface (item 16b, bottom surface of item 16), the protrusion (item A1) being provided at the second surface side (item 16a, upper surface of item 16), the protrusion (item A1) protruding in a first direction perpendicular to the second surface (item 16a, upper surface of item 16); a semiconductor chip (item 12) mounted on the second surface (item 16a, upper surface of item 16) of the base member (item 16) via a first connection member (item 13), the semiconductor chip (item 12) including a first electrode (item 12c), a second electrode (item 12b), a control pad (item 12d), and a semiconductor part (item 12a), the first electrode (item 12c) being provided on a back surface (bottom surface of item 12a) of the semiconductor part (item 12a), the first connection member (item 13) being connected to the first electrode (item 12c), the second electrode (item 12b) and the control pad (item 12d) being provided on a front surface (to surface of item 12a) of the semiconductor part (item 12a), the front surface (top surface of item 12a) being at a side opposite to the back surface (back surface of item 12a) of the semiconductor part (item 12a), the control pad (item 12d) being apart from the second electrode (item 12b), the semiconductor part (item 12a) being positioned between the first electrode (item 12c) and the second electrode (item 12b) and between the first electrode (item 12c) and the control pad (item 12d); and a first conductive member (item 20) bonded on the second electrode (item 12b) of the semiconductor chip (item 12) via a second connection member (item 15), the semiconductor chip (item 12) including a space (space shown but not labeled) between the second electrode (item 12b) and the control pad (item 12d) at the front surface side of the semiconductor part (item 12a), the semiconductor chip (item 12) being mounted so that the protrusion (item A1) of the base member (item 16) and the space (space shown but not labeled) between the second electrode (item 12b) and the control pad (item 12d) overlap in the first direction, but does not specifically disclose the space (space shown but not labeled) between the second electrode (item 12b) and the control pad (item 12b) including a first portion and a second portion, the first portion extending along the front surface of the semiconductor part in a second direction, the second portion extending along the front surface of the semiconductor part in a third direction crossing the second direction, the first portion of the space having a first long-side length in the second direction, the second portion of the space having a second long-side length in the third direction.
As evidenced by Taniguchi (Fig. 2 and associated text) and/or Inumiya (Figs. 1, 2 and associated text) the configuration in which a second electrode (item 10ea, Taniguchi, item 12, Inumiya) is formed to surround at least two sides of a control electrode (item 10g, Taniguchi, item 14, Inumiya) is well known in the art.
It would have been obvious to modify the invention to include a second electrode surrounding a control electrode, since such a modification would have involved a mere change in the configuration/shape of a component for the purpose of not having direct physical contact with one another and design choice. A change in configuration/shape is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)).
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Applicant’s Fig. 3
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Taniguchi’s Fig. 2 (rotated to correlate to the Applicant’s Fig. 3)
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Inumiya Fig. 1 (rotated to correlate to the Applicant’s Fig. 3)
Therefore, Sato (Figs. 2, 3, 5 and associated text) as evidenced/modified by Taniguchi (Fig. 2 and associated text) and/or Inumiya (Figs. 1, 2 and associated text) discloses the space (space shown but not labeled, Sato as modified by the space shown but not labeled of Taniguchi and/or Inumiya) between the second electrode (item 12b, Sato, item 10ea, Taniguchi, item 12, Inumiya) and the control pad (item 12d, Sato, item 10g, Taniguchi, item 14, Inumiya) including a first portion and a second portion, the first portion extending along the front surface of the semiconductor part (item 12a, Sato, item 10, Taniguchi, items 10, 11, Inumiya) in a second direction, the second portion extending along the front surface of the semiconductor part (item 12a, Sato, item 10, Taniguchi, items 10, 11, Inumiya) in a third direction crossing the second direction, the first portion of the space (space shown but not labeled, Sato as modified by the space shown but not labeled of Taniguchi and/or Inumiya) having a first long-side length in the second direction, the second portion of the space (space shown but not labeled, Sato as modified by the space shown but not labeled of Taniguchi and/or Inumiya) having a second long-side length in the third direction, the protrusion (item A1, Sato) of the base member (item 16, Sato) having a first length in the second direction and a second length in the third direction, the first length of the protrusion (item A1, Sato) being equal to or greater than the first long-side length of the first portion of the space (space shown but not labeled, Sato as modified by the space shown but not labeled of Taniguchi and/or Inumiya) between the second electrode (item 12b, Sato, item 10ea, Taniguchi, item 12, Inumiya) and the control pad (item 12d, Sato, item 10g, Taniguchi, item 14, Inumiya), the second length of the protrusion (item A1, Sato) being equal to or greater than the second long-side length of the second portion of the space (space shown but not labeled, Sato as modified by the space shown but not labeled of Taniguchi and/or Inumiya) between the second electrode (item 12b, Sato, item 10ea, Taniguchi, item 12, Inumiya) and the control pad (item 12d, Sato, item 10g, Taniguchi, item 14, Inumiya).
Sato as evidenced/modified by Taniguchi and/or Inumiya does not specifically disclose the protrusion at the second surface and separated from an outer peripheral edge of the second surface…the protrusion being provided inside of an outer peripheral edge of the first electrode in the second direction and third direction.
Niimi (Figs. 1, 3, 9(c), 9(d), 10 and associated text) discloses a base member (item 13) including a first surface (bottom surface of item 13), a second surface (top surface of item 13), and a protrusion (items 22, 23), the second surface (top surface of item 13) being at a side opposite to the first surface (bottom surface of item 13), the protrusion (items 22, 23) at the second surface (top surface of item 13) and separated from an outer peripheral edge of the second surface (top surface item 13), the protrusion (items 22, 23) protruding in a first direction perpendicular to the second surface (top surface item 13)…the protrusion (items 22, 23) being provided inside of an outer peripheral edge of the first electrode (entire lower surface of item 12, “The entire lower surface of the semiconductor chip 12 is an electrode for soldering (a collector electrode when the chip 12 is an IGBT, for example)”) in the second direction and third direction.
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Niimi for the purpose of reducing stress generated at the end of the solder bonded to the electrode on the upper surface of the semiconductor chip, , since such a modification would have involved a mere change in the shape of a component. A change in shape is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)).
In regards to claim 2, Sato (Figs. 2, 3, 5 and associated text) as evidenced/modified by Taniguchi (Fig. 2 and associated text) and/or Inumiya (Figs. 1, 2 and associated text) discloses wherein the first portion of the space (space shown but not labeled, Sato as modified by the space shown but not labeled of Taniguchi and/or Inumiya) between the second electrode (item 12b, Sato, item 10ea, Taniguchi, item 12, Inumiya) and the control pad (item 12d, Sato, item 10g, Taniguchi, item 14, Inumiya) has a first short-side width in the third direction, the first short-side width being less than the second long-side length in the third direction of the second portion of the space (space shown but not labeled, Sato as modified by the space shown but not labeled of Taniguchi and/or Inumiya), and the second portion of the space (space shown but not labeled, Sato as modified by the space shown but not labeled of Taniguchi and/or Inumiya) has a second short-side width in the second direction, the second short-side width being less than the first long-side length in the second direction of the first portion of the space (space shown but not labeled, Sato as modified by the space shown but not labeled of Taniguchi and/or Inumiya).
In regards to claim 3, Sato (Figs. 2, 3, 5 and associated text) discloses wherein the control pad (item 12d) of the semiconductor chip (item 12) overlaps the protrusion (item A1) of the base member (item 16) in the first direction.
In regards to claim 4, Sato (Figs. 2, 3, 5 and associated text) as evidenced/modified by Taniguchi (Fig. 2 and associated text) and/or Inumiya (Figs. 1, 2 and associated text) discloses wherein the second electrode (item 12b, Sato, item 10ea, Taniguchi, item 12, Inumiya) of the semiconductor chip (item 12, Sato, item 10, Taniguchi, item 10, Inumiya) includes an inner portion and an outer edge portion, the outer edge portion extending outward from the inner portion between the semiconductor part (item 12a, Sato, item 10, Taniguchi, items 10, 11, Inumiya) and the second connection member (item 15, Sato, item 32, Inumiya), the outer edge portion extending along the space (space shown but not labeled, Sato as modified by the space shown but not labeled of Taniguchi and/or Inumiya) between the second electrode (item 12b, Sato, item 10ea, Taniguchi, item 12, Inumiya) and the control pad, and the outer edge portion of the second electrode (item 12b, Sato, item 10ea, Taniguchi, item 12, Inumiya) overlaps the protrusion (item A1, Sato) of the base member (item 16, Sato) in the first direction.
In regards to claim 5, Sato (Figs. 2, 3, 5 and associated text) as evidenced/modified by Taniguchi (Fig. 2 and associated text) and/or Inumiya (Figs. 1, 2 and associated text) discloses wherein the semiconductor chip (item 12, Sato, item 10, Taniguchi, item 10, Inumiya) has a quadrilateral shape including four corners facing the base member (item 16, Sato, item 21, Inumiya) via the first connection member (item 13, Sato, item 31), and the control pad (item 12d, Sato, item 10g, Taniguchi, item 14, Inumiya) is provided at one of the four corners.
In regards to claim 9, Sato (Fig. 2, and associated text) discloses wherein the first connection member (item 13) has a first thickness in the first direction and a second thickness in the first direction, the first thickness being defined between the first electrode (item 12c) and a portion (item A2) other than the protrusion (item A1) of the base member (item 16), the second thickness being defined between the first electrode (item 12c) and the protrusion (item A1) of the base member (item 16), and the first thickness is greater than the second thickness.
In regards to claim 6, Sato as evidence/modified by Taniguchi and/or Inumiya does not specifically disclose wherein the base member (item 16, Sato, item 21, Inumiya) further includes a second protrusion facing the semiconductor chip (item 12, Sato, item 10, Taniguchi, item 10, Inumiya)via the first connection member (item 13, Sato)) at another one of the four corners.
Niimi (Figs. 1, 9(c), 9(d) and associated text) discloses wherein the base member (item 13) further includes a second protrusion (items 22, 23) facing the semiconductor chip (item 12) via the first connection member (item 16) at another one of the four corners and/or all four corners. Niimi also discloses the protrusions (items 22, 23) can have various shapes.
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Niimi for the purpose of reducing stress generated at the end of the solder bonded to the electrode on the upper surface of the semiconductor chip, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art (St. Regis Paper Co. v. Bemis Co., 193
USPQ 8).
In regards to claim 7, Sato as evidenced/modified by Taniguchi and/or Inumiya and modified by Niimi (Figs. 1, 9(c), 9(d) and associated text) discloses wherein the base member (item 13) further includes second protrusions (items 22, 23) facing the semiconductor chip (item 12), and the semiconductor chip (item 12) includes three corners facing the second protrusions (items 22, 23), respectively.
In regards to claim 8, Sato as evidenced/modified by Taniguchi and/or Inumiya and modified by Niimi (Figs. 1, 9(c), 9(d) and associated text) discloses wherein the protrusion (items 22, 23) of the base member (item 13) includes a first surface facing the semiconductor chip (item 12) via the first connection member (item 16), the second protrusion (items 22, 23) of the base member (item 13) includes a second surface facing the semiconductor chip (item 12) via the first connection member (item 16), and a first surface area of the first surface is greater than a second surface area of the second surface. Examiner note that Fig. 9(d) discloses an embodiment where the protrusions (item 23) are different sizes and/or shapes and therefore would have different surface areas.
In regards to claim 13, Sato (Figs. 2, 3, 5 and associated text) as evidenced/modified by Taniguchi (Fig. 2 and associated text) and/or Inumiya (Figs. 1, 2 and associated text) discloses a second conductive member bonded (item 27, Inumiya) on the control pad (item 12d, Sato, item 10g, Taniguchi, item 14, Inumiya) of the semiconductor chip (item 12, Sato, item 10, Taniguchi, item 10, Inumiya) via a third connection member (item 34, Inumiya), the protrusion (item A1, Sato) of the base member (item 16, Sato) overlapping a space (space shown but not labeled in Inumiya) between the second connection member (item 32, Inumiya) and the third connection member (item 34, Inumiya) in the first direction.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Onoda et al. (CN 107534032 B, Figs. 7, 10, 11) in regards to the protrusion.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TELLY D GREEN whose telephone number is (571)270-3204. The examiner can normally be reached M-F 8am-5pm.
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TELLY D. GREEN
Examiner
Art Unit 2898
/TELLY D GREEN/Primary Examiner, Art Unit 2898 March 29, 2026
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