DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to the amendments filed on 03/03/2026.
Applicant’s amendments filed 03/03/2026 have been fully considered and reviewed by the examiner. The examiner notes the amendment of claims 1, 12, and 13; and the addition of new claims 21 and 22.
Claim Objections
Claim 12-17 and 22 are objected to because of the following informalities:
Claim 12 recites “the upper surface of semiconductor substrate” (line 20) which should be replaced with “an upper surface of the semiconductor substrate”, to avoid antecedent basis issue.
Claim 12 recites “the same plane” (line 21) which should be replaced with “a same plane”, to avoid antecedent basis issue.
Claim 13 recites “upper surface of the semiconductor substrate” which should be replaced with “the upper surface of the semiconductor substrate”, to avoid antecedent basis issue.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 12-17 and 22 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention
Claim 12 recites limitations “each of the transistors”. There is insufficient antecedent basis for this limitation in the claim because it is unclear whether “each of the transistors” relates back to “a high voltage transistor”, “a low voltage transistor”, and “a very low voltage transistor” (recited in lines 3, 5, and 7, respectively) or to set forth additional transistors.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 7-11, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0359501 to Akaiwa et al. (hereinafter Akaiwa) in view of Chuang et al. (US 2016/0225846, hereinafter Chuang) and Kocon (US 2013/0009225) (the reference US 2022/0059529 to Yeom et al. is presented as evidence, hereinafter Yeom).
With respect to claims 1 and 3, Akaiwa discloses a semiconductor device (e.g., an integrated circuit including low voltage transistors, high voltage transistors, and passive device including a resistor and a capacitor) (Akaiwa, Figs. 14A-14E, ¶0002, ¶0056-¶101), comprising:
a transistor (e.g., a low voltage transistor in a second region 100/200) (Akaiwa, Figs. 14A-14E, ¶0059, ¶0061) including:
a gate insulating film (e.g., 12, in the second region 100/200) (Akaiwa, Figs. 14A-14E, ¶0056, ¶0061, ¶0087) on an upper surface of a semiconductor substrate (2) and including a dielectric film (e.g., silicon oxide), and
a gate electrode (e.g., 40, elemental metal W or Ti or metallic material) (Akaiwa, Figs. 14A-14E, ¶0072, ¶0080, ¶0087) on an upper surface of the gate insulating film (12), the gate electrode (40) being a metal material; and
a capacitance element (e.g., a capacitor in the capacitor region 800) (Akaiwa, Figs. 14A-14E, ¶0059, ¶0061) including:
a first insulating film (e.g., 12, in the capacitor region 800) (Akaiwa, Figs. 14A-14E, ¶0101) on the upper surface of the semiconductor substrate (2) at a same height as the gate insulating film (12, in the second region 100/200),
a first conductive layer (e.g., 34) (Akaiwa, Figs. 14A-14E, ¶0068, ¶0101) on an upper surface of the first insulating film (12),
a second insulating film (e.g., 13) (Akaiwa, Figs. 14A-14E, ¶0101), and
a second conductive layer (e.g., 40, elemental metal W or Ti or metallic material) (Akaiwa, Figs. 14A-14E, ¶0072, ¶0101), wherein
the second conductive layer (40, in the capacitor region 800) is the same metal material as the gate electrode (40, in the second region 100/200), and the first conductive layer (34) is a conductive material (e.g., polysilicon material) (Akaiwa, Figs. 14A-14E, ¶0068, ¶0101) having a higher resistance (e.g., as evidenced by Yeom (¶0006), polysilicon used as a gate material has a higher resistance than most metals) than the metal material of the second conductive layer (40) (as claimed in claim 1);
wherein the transistor (e.g.,100/200) and the capacitance element (800) are electrically isolated from one another by an element isolation region (e.g., trench isolation structure 8) (Akaiwa, Figs. 14A-14E, ¶0066) provided in the semiconductor substrate (2) (as claimed in claim 3).
Further, Akaiwa does not specifically disclose a resistance-capacitance element including: a second insulating film on an upper surface of the first conductive layer, a third insulating film on an upper surface of the second insulating film, and a second conductive layer on an upper surface of the third insulating film, wherein the third insulating film includes the dielectric film of the gate insulating film (as claimed in claim 1 and claim 3).
However, Chuang teaches forming a semiconductor device (e.g., an integrated circuit including flash memory cell, logic devices, and a capacitor) (Chuang, Figs. 1, 4, ¶0011-¶0021, ¶0064-¶0065) comprising a capacitance element including stacked capacitors (e.g., a first capacitor C1 and a second capacitor C2) (Chuang, Figs. 1, 4, ¶0014, ¶0021) and contacts (Chuang, Figs. 1, 4, ¶0014) coupled to the top electrode (120) and the substrate (150). The capacitance element of Chuang includes a first insulating film (e.g., a first capacitor dielectric 125 made of SiO2) (Chuang, Figs. 1, 4, ¶0021) on the upper surface of the semiconductor substrate (102), a first conductive layer (e.g., bottom capacitor electrode 118) (Chuang, Figs. 1, 4, ¶0021) on an upper surface of the first insulating film (125), a second insulating film (e.g., a capacitor dielectric 122, same as the logic gate dielectric 128, including oxide layer 142) (Chuang, Figs. 1, 4, ¶0018, ¶0021) on an upper surface of the first conductive layer (118), a third insulating film (e.g., the capacitor dielectric 122, same as the logic gate dielectric 128, including a high k dielectric layer 144 on the oxide layer 142) on an upper surface of the second insulating film (e.g., the oxide layer 142 of the capacitor dielectric 122), and a second conductive layer (120) (Chuang, Figs. 1, 4, ¶0021) on an upper surface of the third insulating film (e.g., the high k dielectric layer 144 of the capacitor dielectric 122), wherein the third insulating film (e.g., the high k dielectric layer 144 of the capacitor dielectric 122 that is the same as the logic gate dielectric 128) (Chuang, Fig. 4, ¶0018, ¶0021) includes the dielectric film (144) of the gate insulating film (e.g., logic gate dielectric 128 including high k dielectric layer 144). The integrated circuit of Chuang comprising memory device and capacitor is compatible with high k metal gate (HKMG) technology, and is configured to improve performance and reliability of the integrated circuit (Chuang, Figs. 1, 4, ¶0011-¶0014).
Further, Kocon teaches forming an integrated resistance-capacitance element (146/438) (Kocon, Figs. 1C, 4B, ¶0004, ¶0010, ¶0013-¶0030, ¶0046-¶0050) including a capacitor (126/426) and a resistor (142/434) by forming electrical contacts to the capacitor electrode and the doped substrate region, wherein the integrated resistance-capacitance element is formed in the active region isolated with isolation regions (e.g., trench oxide STI regions or LOCOS oxidation regions 104/404) (Kocon, Figs. 1C, 4B, ¶0013, ¶0046), and the electrical contacts are connected with the conductive layer or wiring that functions as a resistor, to provide the integrated resistance-capacitance element to control undesired voltage oscillations of the integrated circuit (Kocon, ¶0002, ¶0004, ¶0010, ¶0030, ¶0049-¶0050).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Akaiwa by forming a stacked capacitor element integrated with the memory device and having contacts coupled to the top electrode as taught by Chuang, and forming a resistor concurrently with a capacitor plate as taught by Kocon, wherein the resistor includes electrical contacts connected to the capacitor electrode of Chuang and a conductive layer or wiring that functions as a resistor to have the semiconductor device, comprising: a resistance-capacitance element including: a second insulating film on an upper surface of the first conductive layer, a third insulating film on an upper surface of the second insulating film, and a second conductive layer on an upper surface of the third insulating film, wherein the third insulating film includes the dielectric film of the gate insulating film, in order to provide an improved integrated circuit comprising memory device and a capacitor compatible with high k metal gate (HKMG) technology to improve performance and reliability of the integrated circuit; and to provide improved integrated circuit capable of controlling the undesired voltage oscillations of the integrated circuit (Chuang, ¶0011-¶0014; Kocon, ¶0002, ¶0004, ¶0010, ¶0030, ¶0049-¶0050).
Regarding claim 2, Akaiwa in view of Chuang and Kocon discloses the semiconductor device according to claim 1. Further, Akaiwa discloses the semiconductor device, wherein the conductive material (34) is polysilicon (Akaiwa, Figs. 14A-14E, ¶0068, ¶0101), but does not specifically disclose that the second insulating film is a silicon oxide film.
However, Chuang teaches that the second insulating film (e.g., the high temperature oxide layer 142 of the capacitor dielectric 122, same as the logic gate dielectric 128) (Chuang, Fig. 4, ¶0018, ¶0021) is a silicon oxide film (e.g., the high temperature oxide layer 142 is formed by oxidizing a portion of the underlying polysilicon 118).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Akaiwa/Chuang/Kocon by forming a stacked capacitor element as taught by Chuang to have the semiconductor device, wherein the second insulating film is a silicon oxide film, in order to provide an improved integrated circuit comprising memory device and a capacitor compatible with high k metal gate (HKMG) technology to improve performance and reliability of the integrated circuit (Chuang, ¶0011-¶0014).
Regarding claim 7, Akaiwa in view of Chuang and Kocon discloses the semiconductor device according to claim 1. Further, Akaiwa discloses the semiconductor device, wherein an uppermost surface of the gate electrode (40, in the second region 100/200) (Akaiwa, Figs. 14A-14E, ¶0072, ¶0101) and an uppermost surface of the second conductive layer (40, in the capacitor region 800) are at a same height from the semiconductor substrate (2).
Regarding claims 8 and 9, Akaiwa in view of Chuang and Kocon discloses the semiconductor device according to claim 1. Further, Akaiwa does not specifically disclose that the dielectric film is a high-k dielectric material (as claimed in claim 8); wherein the dielectric film is hafnium silicate (as claimed in claim 9).
However, Chuang teaches the semiconductor device, wherein the dielectric film (e.g., the logic gate dielectric 128, including high k dielectric layer 144) (Chuang, Fig. 4, ¶0018, ¶0021) is a high-k dielectric material, and includes hafnium silicate (HfSiO).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Akaiwa/Chuang/Kocon by forming a stacked capacitor element as taught by Chuang to have the semiconductor device, wherein the dielectric film is a high-k dielectric material (as claimed in claim 8); wherein the dielectric film is hafnium silicate (as claimed in claim 9), in order to provide an improved integrated circuit comprising memory device and a capacitor compatible with high k metal gate (HKMG) technology to improve performance and reliability of the integrated circuit (Chuang, ¶0011-¶0014).
Regarding claim 10, Akaiwa in view of Chuang and Kocon discloses the semiconductor device according to claim 9. Further, Akaiwa discloses the semiconductor device, wherein the metal material (e.g., 40, elemental metal W) (Akaiwa, Figs. 14A-14E, ¶0072, ¶0080, ¶0087) is tungsten (W), and the conductive material (34) (Akaiwa, Figs. 14A-14E, ¶0068, ¶0101) is polysilicon.
Regarding claim 11, Akaiwa in view of Chuang and Kocon discloses the semiconductor device according to claim 1. Further, Akaiwa discloses the semiconductor device, wherein the metal material (e.g., 40, elemental metal W) (Akaiwa, Figs. 14A-14E, ¶0072, ¶0080, ¶0087) is tungsten (W), and the conductive material (34) (Akaiwa, Figs. 14A-14E, ¶0068, ¶0101) is polysilicon.
Regarding claim 21, Akaiwa in view of Chuang and Kocon discloses the semiconductor device according to claim 1. Further, Akaiwa discloses the semiconductor device, wherein the dielectric film of the gate insulating film (12) (Akaiwa, Figs. 14A-14E, ¶0056, ¶0061, ¶0087) directly contacts the upper surface of the semiconductor substrate (2).
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0359501 to Akaiwa) in view of Chuang (US 2016/0225846) and Kocon (US 2013/0009225) as applied to claim 1, and further in view of Park (US 2015/0357377).
Regarding claim 4, Akaiwa in view of Chuang and Kocon discloses the semiconductor device according to claim 1. Further, Akaiwa does not specifically disclose a first contact plug electrically connected to the first conductive layer,a second contact plug electrically connected to the second conductive layer, and a third contact plug electrically connected to the semiconductor substrate. However, Park teaches forming a stacked capacitor (Park, Fig. 8, ¶0025-¶0037) having a large capacity to improve signal transfer characteristics, wherein a first power voltage terminal (V1) is applied to the second conductive layer (125/130), a second power voltage terminal (V2) is applied to the first conductive layer (115), and a third power voltage terminal (V3) is applied to the substrate bias region (140).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Akaiwa/Chuang/Kocon by forming a plurality of contact plugs connected to the first conductive layer and the second conductive layer of the stacked capacitor as taught by Park to have the semiconductor device, wherein a first contact plug electrically connected to the first conductive layer, a second contact plug electrically connected to the second conductive layer, and a third contact plug electrically connected to the semiconductor substrate, in order to provide a multi-stage capacitor having a large capacity to improve signal transfer characteristics (Park, ¶0007-¶0011, ¶0033, ¶0037).
Regarding claim 5, Akaiwa in view of Chuang, Kocon, and Park discloses the semiconductor device according to claim 4. Further, Akaiwa does not specifically disclose that a surface area of the second conductive layer is smaller than a surface area of the first conductive layer, and the first contact plug is connected to a portion of the upper surface of the first conductive layer not covered by the second conductive layer.
However, Park teaches forming the stacked capacitor (Park, Fig. 8, ¶0025-¶0037), wherein a surface area of the second conductive layer (125) is smaller than a surface area of the first conductive layer (115), and the second power voltage terminal (V2) is connected to a portion of the upper surface of the first conductive layer (115) not covered by the second conductive layer (125/130).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Akaiwa/Chuang/Kocon/Park by forming a plurality of contact plugs connected to the first conductive layer and the second conductive layer of the stacked capacitor as taught by Park to have the semiconductor device, wherein a surface area of the second conductive layer is smaller than a surface area of the first conductive layer, and the first contact plug is connected to a portion of the upper surface of the first conductive layer not covered by the second conductive layer, in order to provide a multi-stage capacitor having a large capacity to improve signal transfer characteristics (Park, ¶0007-¶0011, ¶0033, ¶0037).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0359501 to Akaiwa) in view of Chuang (US 2016/0225846), Kocon (US 2013/0009225), and Park (US 2015/0357377) as applied to claim 4, and further in view of Ariyoshi et al. (US 2012/0034751, hereinafter Ariyoshi).
Regarding claim 6, Akaiwa in view of Chuang, Kocon, and Park discloses the semiconductor device according to claim 4. Further, Akaiwa does not specifically disclose that the first contact plug is in a through via hole that penetrates the second conductive layer, the second insulating film, and the third insulating film and reaches the first conductive layer.
However, Ariyoshi teaches forming an integrated circuit (Ariyoshi, Fig. 2K, ¶0015-¶0019, ¶0113-¶0115, ¶0162-¶0167, ¶0176-¶0179) comprising a flash memory cell region (I) and a capacitor region (II) including a capacitor having a first conductive layer (11a) and a second conductive layer (30a), wherein the first contact plug (58a) is in a through via hole (30c) that penetrates the second conductive layer (30a), the second insulating film (14a), and reaches the first conductive layer (11a), the first contact plug (58a) controls the potential of the lower electrode (11a) of the capacitor and the second contact plug (58b) controls the potential of the upper electrode (30a) of the capacitor, wherein the opening (30c) of the upper electrode (30a) has a reduced diameter that allows the semiconductor device to be reduced in size while maintaining the capacitance of the capacitor (Ariyoshi, Fig. 2K, ¶0002-¶0004, ¶0015-¶0019, ¶0167, ¶0179).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Akaiwa/Chuang/Kocon/Park by forming an opening of the upper electrode for the contact plug as taught by Ariyoshi, wherein the opening extends through the second conductive layer and underlying insulating layer including the second insulating film and the third insulating film, and exposes the first conductive layer to have the semiconductor device, wherein the first contact plug is in a through via hole that penetrates the second conductive layer, the second insulating film, and the third insulating film and reaches the first conductive layer, in order to provide improved semiconductor device with reduced size while maintaining the capacitance of the capacitor (Ariyoshi, ¶0002-¶0004, ¶0015-¶0019, ¶0167, ¶0179).
Claims 12-17 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0359501 to Akaiwa in view of Chuang (US 2016/0225846), Kocon (US 2013/0009225), Tsai et al. (US Patent No. 9,589,846, hereinafter Tsai), and Lin et al. (US 2010/0052074, hereinafter Lin).
With respect to claim 12, Akaiwa discloses a semiconductor device (e.g., an integrated circuit including low voltage transistors, high voltage transistors, and passive device including a resistor and a capacitor) (Akaiwa, Figs. 14A-14E, ¶0002, ¶0056-¶101), comprising:
a semiconductor substrate (2/4) (Akaiwa, Figs. 14A-14E, ¶0056-¶0058);
a high voltage transistor (e.g., p-type and n-type field effect transistors) (Akaiwa, Figs. 14A-14E, ¶0059, ¶0061) in a first region (500/600) of the semiconductor substrate (2/4);
a low voltage transistor (e.g., p-type and n-type field effect transistors) (Akaiwa, Figs. 14A-14E, ¶0059, ¶0061) in a second region (100/200) of the semiconductor substrate (2/4);
a very low voltage transistor (e.g., p-type and n-type field effect transistors) (Akaiwa, Figs. 14A-14E, ¶0059, ¶0061) in a third region (300/400) of the semiconductor substrate (2/4);
a passive element (e.g., a resistor and a capacitor) (Akaiwa, Figs. 14A-14E, ¶0059, ¶0061) in a fourth region (700/800) of the semiconductor substrate, the passive element (700/800) being configurable as a capacitor, and a resistor; and
an interlayer insulator (70) (Akaiwa, Figs. 14A-14E, ¶0095-¶0096) covering the high voltage transistor (500/600), the low voltage transistor (100/200), the very low voltage transistor (300/400), and the passive element (700/800), wherein
each of the transistors (500/600, 100/200, and 300/400) includes a gate electrode (40 and 25/26) (Akaiwa, Figs. 14A-14E, ¶0090-¶0093, ¶0098-¶100), a first dielectric film (10/13 and 12) on bottom of the gate electrode (40 and 25/26),
the high voltage transistor (500/600) having a gate oxide layer (10/20L) of a first thickness (between 4 nm and 30 nm) (Akaiwa, Figs. 14A-14E, ¶0061, ¶0098-¶100) between the bottom surface of the gate electrode (40) and the semiconductor substrate (2/4), and
the low voltage transistor (100/200) (Akaiwa, Figs. 14A-14E, ¶0061, ¶0098-¶100) having a gate oxide layer (12/22L) of a second thickness (between 1.5 nm and 3 nm), less than the first thickness, between the bottom surface of the gate electrode (25/26) and the semiconductor substrate (2/4), and
the upper surface of semiconductor substrate (2) in second (100/200), third (300/400), and fourth (800) regions is the same plane (e.g., as shown in Fig. 2B, the upper surface of the semiconductor substrate 2 is in a same plane in the second region 100/200, the third region 300/400, and the fourth region 800 for the devices in Fig. 14B) (Akaiwa, Figs. 14A-14E, ¶0061).
Further, Akaiwa does not specifically disclose (1) a resistance-capacitance element, the resistance-capacitance element being configurable as a first-type capacitor, a second-type capacitor, and a resistor; (2) each of the transistors includes a first high-k dielectric film on bottom and side surfaces of the gate electrode, and a first interlayer film on bottom and side surfaces of the first high-k dielectric film.
Regarding (1), Chuang discloses a semiconductor device (e.g., an integrated circuit including flash memory cell, logic devices, and a capacitor) (Chuang, Figs. 1, 4, ¶0011-¶0021, ¶0064-¶0065) comprising a capacitance element including stacked capacitors (e.g., a first capacitor C1 and a second capacitor C2) (Chuang, Figs. 1, 4, ¶0014, ¶0021) and contacts (Chuang, Figs. 1, 4, ¶0014) coupled to the top electrode (120) and the substrate (150), to provide an improved integrated circuit comprising memory device and capacitor compatible with high k metal gate (HKMG) technology to improve performance and reliability of the integrated circuit (Chuang, Figs. 1, 4, ¶0011-¶0014).
Further, Kocon teaches forming an integrated resistance-capacitance element (146/438) (Kocon, Figs. 1C, 4B, ¶0004, ¶0010, ¶0013-¶0030, ¶0046-¶0050) including a capacitor (126/426) and a resistor (142/434) by forming electrical contacts to the capacitor electrode and the doped substrate region, wherein the integrated resistance-capacitance element is formed in the active region isolated with isolation regions (e.g., trench oxide STI regions or LOCOS oxidation regions 104/404) (Kocon, Figs. 1C, 4B, ¶0013, ¶0046), and the electrical contacts are connected with the conductive layer or wiring that functions as a resistor, to provide the integrated resistance-capacitance element to control undesired voltage oscillations of the integrated circuit (Kocon, ¶0002, ¶0004, ¶0010, ¶0030, ¶0049-¶0050).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Akaiwa by forming a stacked capacitor element integrated with the memory device and having contacts coupled to the top electrode as taught by Chuang, and forming a resistor concurrently with a capacitor plate as taught by Kocon, wherein the resistor includes electrical contacts connected to the capacitor electrode of Chuang and a conductive layer or wiring that functions as a resistor to have the semiconductor device, comprising: a resistance-capacitance element, the resistance-capacitance element being configurable as a first-type capacitor, a second-type capacitor, and a resistor, in order to provide an improved integrated circuit comprising memory device and a capacitor compatible with high k metal gate (HKMG) technology to improve performance and reliability of the integrated circuit; and to provide improved integrated circuit capable of controlling the undesired voltage oscillations of the integrated circuit (Chuang, ¶0011-¶0014; Kocon, ¶0002, ¶0004, ¶0010, ¶0030, ¶0049-¶0050).
Regarding (2), Tsai teaches forming a reliable integrated circuit (Tsai, Fig. 9, Col. 1, lines 48-67; Col. 3, lines 2-67; Cols. 4-5) including a low voltage transistor (502) and a high voltage transistor (402) comprising a high-k gate dielectric layer (317) (Tsai, Fig. 9, Col. 5, lines 26-34) having U-shape on the first oxide layer (507/404) (Tsai, Fig. 9, Col. 5, lines 21-22) having different thickness, wherein each of the transistors (502 and 402) includes a first high-k dielectric film (317) on bottom and side surfaces of the gate electrode (320).
Further, Lin teaches forming a metal gate transistor (Lin, Fig. 8, ¶0026-¶0035) comprising a gate dielectric layer including a high-k gate dielectric layer (54) and a cap layer (56) including another high-k material (e.g., lanthanide oxides or aluminum oxide) such that a first high-k gate dielectric layer (54) is formed on bottom and side surfaces of the cap high-k dielectric film (56), to define a work function of the metal layer of the N-type or P-type transistor to improve performance of the CMOS transistors.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Akaiwa by forming a high-k gate dielectric layer having U-shape on the first oxide layer for the low voltage transistor and the high voltage transistor as taught by Tsai, wherein the U-shaped high-k gate dielectric layer includes a first gate dielectric layer and a cap high-k dielectric layer as taught by Lin, the first gate dielectric layer of Lin is a first interlayer between the first oxide layer and the cap high-k gate dielectric to have the semiconductor device, wherein each of the transistors includes a first high-k dielectric film on bottom and side surfaces of the gate electrode, and a first interlayer film on bottom and side surfaces of the first high-k dielectric film, in order to provide a reliable integrated circuit with controlled work function of the gate metal to improve performance of the CMOS transistors (Tsai, Col. 1, lines 48-67; Lin, ¶0008-¶0010, ¶0026-¶0035).
Regarding claim 13, Akaiwa in view of Chuang, Kocon, Tsai, and Lin discloses the semiconductor device according to claim 12. Further, Akaiwa discloses the semiconductor device, wherein the passive element (700/800) has: a first insulating film (12) (Akaiwa, Figs. 14A-14E, ¶0061, ¶0081, ¶0098) on upper surface of the semiconductor substrate (2), the first insulating film (12) having the second thickness and being a same material as the gate oxide film (12) of the low voltage transistor (100/200), but does not specifically disclose that the resistance-capacitance element has: a first conductive layer on the first insulating film and formed of polysilicon; a stopper layer on the first conductive layer, the stopper layer being formed of insulator material; a second interlayer film on the stopper layer, the second interlayer film being formed of the same material as the first interlayer film; a second high-k dielectric film on the second interlayer film, the second high-k dielectric film being formed of the same material as the first high-k dielectric film; and a second conductive layer on the second high-k dielectric film, the second conductive layer being formed of the same material as the gate electrode.
However, Chuang teaches forming the capacitance element (e.g., stacked capacitors including a first capacitor C1 and a second capacitor C2) (Chuang, Fig. 4, ¶0014, ¶0021) including a first insulating film (e.g., a first capacitor dielectric 125 made of silicon oxide) (Chuang, Fig. 4, ¶0021) on the upper surface of the semiconductor substrate (102), a first conductive layer (118) on the first insulating film (125) and formed of polysilicon; a stopper layer (e.g., etch stop layer (ESL) 146) on the first conductive layer (118), the stopper layer (e.g., ESL 146) being formed of insulator material (e.g., the dielectric layer 128 made up of layers 142, 144, and 146) (Chuang, Fig. 4, ¶0018); a second interlayer film (142) on the stopper layer (e.g., on the bottom of the ESL 146), the second interlayer film (142) being formed of the same material as the first interlayer film (e.g., silicon oxide); a second high-k dielectric film (144) on the second interlayer film (142), the second high-k dielectric film (144) being formed of the same material as the first high-k dielectric film (e.g., 144, of the logic dielectric layer 128); and a second conductive layer (120) (Chuang, Fig. 4, ¶0021) on the second high-k dielectric film (144), the second conductive layer (120) being formed of the same material as the gate electrode (148).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Akaiwa/Chuang/Kocon/ Tsai/Lin by forming a stacked capacitor element integrated with the memory device and having contacts coupled to the top electrode as taught by Chuang, and forming a resistor concurrently with a capacitor plate as taught by Kocon to have the semiconductor device, wherein the resistance-capacitance element has: a first conductive layer on the first insulating film and formed of polysilicon; a stopper layer on the first conductive layer, the stopper layer being formed of insulator material; a second interlayer film on the stopper layer, the second interlayer film being formed of the same material as the first interlayer film; a second high-k dielectric film on the second interlayer film, the second high-k dielectric film being formed of the same material as the first high-k dielectric film; and a second conductive layer on the second high-k dielectric film, the second conductive layer being formed of the same material as the gate electrode, in order to provide an improved integrated circuit comprising memory device and capacitor compatible with high k metal gate (HKMG) technology to improve performance and reliability of the integrated circuit; and to provide improved integrated circuit capable of controlling the undesired voltage oscillations of the integrated circuit (Chuang, ¶0011-¶0014; Kocon, ¶0002, ¶0004, ¶0010, ¶0030, ¶0049-¶0050).
Regarding claim 14, Akaiwa in view of Chuang, Kocon, Tsai, and Lin discloses the semiconductor device according to claim 13. Further, Akaiwa does not specifically disclose that the second high-k dielectric film and the second interlayer film are on a sidewall of the second conductive layer.
However, Chuang teaches forming the second high-k dielectric film (e.g., high-k dielectric layer 144 of the dielectric layer 122) as the logic high-k dielectric layer (e.g., high-k dielectric layer 144 of the logic dielectric layer 128).
Further, Lin teaches forming a metal gate transistor (Lin, Fig. 8, ¶0026-¶0035) comprising a gate dielectric layer including a high-k gate dielectric layer (54) and a cap layer (56) including another high-k material (e.g., lanthanide oxides or aluminum oxide) such that a first high-k gate dielectric layer (54) and the cap high-k dielectric film (56) are on a sidewall of the conductive layer (62), to define a work function of the metal layer of the N-type or P-type transistor to improve performance of the CMOS transistors.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Akaiwa/Chuang/Kocon/ Tsai/Lin by forming the second high-k dielectric film and the second interlayer film of the resistance-capacitance element as the first high-k dielectric film and the first interlayer film of a transistor as taught by Chuang, wherein the second high-k dielectric film and the second interlayer film have U-shape as taught by Lin to have the semiconductor device, wherein the second high-k dielectric film and the second interlayer film are on a sidewall of the second conductive layer, in order to provide an improved integrated circuit comprising memory device and capacitor compatible with high k metal gate (HKMG) technology to improve performance and reliability of the integrated circuit; and to control work function of the gate metal to improve performance of the CMOS transistors (Chuang, ¶0011-¶0014; Lin, ¶0008-¶0010, ¶0026-¶0035).
Regarding claim 15, Akaiwa in view of Chuang, Kocon, Tsai, and Lin discloses the semiconductor device according to claim 13. Further, Akaiwa does not specifically disclose that a planar area of the second conductive layer is less than a planar area of the first conductive layer.
However, Chuang teaches forming the stacked capacitors (Chuang, Fig. 4, ¶0014, ¶0021), wherein a planar area of the second conductive layer (120) is less than a planar area of the first conductive layer (118), to provide a capacitor compatible with high k metal gate (HKMG) technology.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Akaiwa/Chuang/Kocon/ Tsai/Lin by forming a stacked capacitor element integrated with the memory device and having contacts coupled to the top electrode as taught by Chuang to have the semiconductor device, wherein a planar area of the second conductive layer is less than a planar area of the first conductive layer, in order to provide an improved integrated circuit comprising memory device and a capacitor compatible with high k metal gate (HKMG) technology to improve performance and reliability of the integrated circuit (Chuang, ¶0011-¶0014).
Regarding claim 16, Akaiwa in view of Chuang, Kocon, Tsai, and Lin discloses the semiconductor device according to claim 13. Further, Akaiwa discloses the semiconductor device, further comprising: a plurality of contacts (e.g., contact via structures 76A, 76G, 86A, 86G, 96A, 96G, 96R, 96C) (Akaiwa, Figs. 14A-14E, ¶0097) extending vertically in the interlayer insulator (70) to an upper surface of the interlayer insulator (70).
Regarding claim 17, Akaiwa in view of Chuang, Kocon, Tsai, and Lin discloses the semiconductor device according to claim 13. Further, Akaiwa does not specifically disclose that an uppermost surface of each gate electrode is at a same height as an uppermost surface of the second conductive layer.
However, Chuang teaches forming the integrated circuit including flash memory cell, logic devices, and a stacked capacitor element (Chuang, Figs. 1, 4, ¶0011-¶0021, ¶0064-¶0065), wherein an uppermost surface of each gate electrode (e.g., 136/138, 120, and 148) is at a same height as an uppermost surface of the second conductive layer (120).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Akaiwa/Chuang/Kocon/ Tsai/Lin by forming the integrated circuit including a plurality of transistors and a stacked capacitor element as taught by Chuang to have the semiconductor device, wherein an uppermost surface of each gate electrode is at a same height as an uppermost surface of the second conductive layer, in order to provide an improved integrated circuit comprising memory device and a capacitor compatible with high k metal gate (HKMG) technology to improve performance and reliability of the integrated circuit (Chuang, ¶0011-¶0014).
Regarding claim 22, Akaiwa in view of Chuang, Kocon, Tsai, and Lin discloses the semiconductor device according to claim 12. Further, Akaiwa discloses the semiconductor device, wherein the upper surface of the semiconductor substrate (2) (Akaiwa, Figs. 14B, ¶0094-¶0101) in the first region (500/600) is in a different plane (e.g., the upper surface of the substrate 2 is lower in the first region 500/600 than that in the second to fourth regions) from that of the upper surface of the semiconductor substrate (2) in second (100/200), third (300/400), and fourth (800) regions.
Response to Arguments
Applicant's arguments filed 03/03/2026 have been fully considered but they are not persuasive.
In response to Applicant’s argument regarding rejection under 35 U.S.C. § 112(b) that “[n]o confusion arises in this context because nothing else other than the three previously recited "transistors" could be intended by "each of the transistors" and those of ordinary skill are able to reasonable ascertain the meaning of claim 12 by basic skills of reading comprehension if nothing else”, the examiner submits that the limitation “a high voltage transistor” (similarly, a low voltage transistor and a very low voltage transistor) is interpreted as “one or more” because the claim uses an open ended transition phrase “comprising”. Thus, it is unclear whether “each of the transistors” relates back to “a high voltage transistor”, “a low voltage transistor”, “a very low voltage transistor”, any combination of three previously recited transistors, or to set forth additional transistors. Thus, the above Applicant’s argument is not persuasive, and the rejection of claim 12 under 35 U.S.C. § 112(b) is maintained.
In response to Applicant’s argument that Chuang does not teach the limitations "a first insulating film on the upper surface of the semiconductor substrate at a same height as the gate insulating film" recited in the amended claim 1, the examiner submits that Akaiwa teaches a passive element (800) including a capacitor having "a first insulating film” (12) on the upper surface of the semiconductor substrate at a same height as “the gate insulating film" (12) of the transistor (100/200), as required by the amended claim 1. Specifically, Fig. 2B of Akaiwa shows that a first gate dielectric layer (22L) is formed on an upper surface of the semiconductor substrate (2/4) at a same height for the transistor elements (100-400) and the passive elements (700/800). The gate dielectric layer (12) in Fig. 14B is patterned portion of the first gate dielectric layer (22) corresponding to each of the transistor elements (100-400) and the passive elements (700/800). Thus, "a first insulating film” (of the capacitance element of Akaiwa) is on the upper surface of the semiconductor substrate “at a same height as the gate insulating film" (of a transistor of Akaiwa), as required by the amended claim 1. Therefore, the above Applicant’s argument is not persuasive, and the rejection of claim 1 under U.S.C. § 103 over Akaiwa is maintained.
In response to Applicant’s argument “[t]he examples in Akaiwa have different circuit elements at various substrate heights and the arrangements of the passive elements (700/800) being a different (higher) levels than transistor elements (100 - 600)”, the examiner submits that in Akaiwa, “the arrangements of the passive elements (700/800)” is at the same level as the transistor elements (100 - 400), and the transistor elements (500 - 600) are at a lower level than the passive elements (700/800) and the transistor elements (100 - 400). Specifically, Fig. 2B of Akaiwa shows that a first gate dielectric layer (22L) is formed on an upper surface of the semiconductor substrate (2/4) arranged in “the same plane” for the transistor elements (100-400) and the passive elements (700/800). The first gate dielectric layer (12) in Fig. 14B is patterned portion of the first gate dielectric layer (22) corresponding to each of the transistor elements (100-400) and the passive elements (700/800). The transistor elements (100-200) correspond to a low voltage transistor in a second region, and the transistor elements (300-400) correspond to a very low voltage transistor in a third region, and the passive elements (700/800) correspond to a capacitance element in a fourth region. In Akaiwa, the upper surface (e.g., in direct contact with the gate dielectric layer 12) of semiconductor substrate (2/4) in second, third, and fourth regions is the same plane, as required by claim 12. Thus, the above Applicant’s argument is not persuasive, and the rejection of claim 12 under U.S.C. § 103 over Akaiwa is maintained.
Regarding dependent claims 2-11, 13-17, and 21-22 which depend on the independent claims 1 and 12, the examiner respectfully submits that the applicant’s arguments with respect to dependent claims are not persuasive for the above reasons, thus, the rejections of the dependent claims are sustained.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATALIA GONDARENKO whose telephone number is (571)272-2284. The examiner can normally be reached 9:30 AM-7:30 PM.
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/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891