DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 08/07/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 7-8, 11, 21, and 23 are rejected under 35 U.S.C. 103 as being unpatentable over US 2007/0267705 to Won et al. (hereinafter Won) in view of Cheng et al. (US Patent No. 8,659,066, hereinafter Cheng).
With respect to claim 1, Won discloses a semiconductor device (e.g., an integrated circuit including a transistor and a capacitor) (Won, Fig. 1F, ¶0008, ¶0064-¶0081), comprising:
a transistor (e.g., active region 92 including a transistor 94) (Won, Fig. 1F, ¶0065, ¶0070) including:
a gate insulating film (e.g., 110a) (Won, Fig. 1F, ¶0070) on an upper surface of a semiconductor substrate (100) and including a dielectric film (e.g., gate oxide), and
a gate electrode (e.g., 120a) (Won, Fig. 1F, ¶0070) on an upper surface of the gate insulating film (110a), the gate electrode (120a) being a polysilicon material; and
a resistance-capacitance element (e.g., a low resistance capacitor) (Won, Fig. 1F, ¶0065, ¶0078-¶0079) including:
a first insulating film (e.g., 110b) (Won, Fig. 1F, ¶0070) on the upper surface of the semiconductor substrate (100) at a same height as the gate insulating film (110a),
a first conductive layer (e.g., 120b) (Won, Fig. 1F, ¶0070) on an upper surface of the first insulating film (110b),
a second insulating film (e.g., a dielectric layer 170 including an oxide film of the oxide-nitride-oxide structure) (Won, Fig. 1F, ¶0077),
a third insulating film (e.g., a dielectric layer 170 including another oxide film of the oxide-nitride-oxide structure) (Won, Fig. 1F, ¶0077) on an upper surface of the second insulating film (e.g., the oxide film of the oxide-nitride-oxide structure), and
a second conductive layer (e.g., 180) (Won, Fig. 1F, ¶0078) on an upper surface of the third insulating film (e.g., another oxide film of the oxide-nitride-oxide structure) (Won, Fig. 1F, ¶0077), wherein
the third insulating film includes a dielectric film (e.g., another oxide film of the oxide-nitride-oxide structure) (Won, Fig. 1F, ¶0077),
the third insulating film (170) is on a side surface of the second conductive layer (180) (Won, Fig. 1F, ¶0077-¶0078),
the second conductive layer (e.g., 180) (Won, Fig. 1F, ¶0078) is a metal material, and
the first conductive layer (120b) is a conductive material (e.g., a polysilicon material) (Won, Fig. 1F, ¶0070, ¶0078-¶0079, ¶0003) having a higher resistance (e.g., metal electrode 180 has a low resistance relative to the polysilicon electrode of the conventional capacitor employing the polysilicon) than the metal material of the second conductive layer (180).
Further, Won does not specifically disclose that the gate electrode being a metal electrode, wherein the third insulating film includes the dielectric film of the gate insulating film, the second conductive layer is the same metal material as the gate electrode.
However, Cheng teaches forming a semiconductor device including a transistor and a capacitor, wherein the gate electrode (750) (Cheng, Fig. 8, Col. 7, lines 31-36; Col. 8, lines 9-16) being a metal electrode (e.g., a metal gate), wherein the interfacial layer (Cheng, Fig. 8, Col. 7, lines 37-51) comprised of silicon oxide/silicon nitride is formed before forming high-k gate layer, and the second conductive layer (752) of the capacitor is the same metal material (750) as the gate electrode of the transistor, to provide an integrated circuit including a high-k/metal gate FET and a low resistance capacitor with improved capacitor’s electrical characteristics fabricated simultaneously (Cheng, Col. 3, lines 59-67; Col. 8, lines 9-16).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Won by forming a transistor and a capacitor including a conductive metal layer as taught by Cheng, wherein the first insulating film of Won includes a silicon oxide layer used as an interfacial layer between the semiconductor material and high-k dielectric to have the semiconductor device, comprising: the gate electrode being a metal electrode, wherein the third insulating film includes the dielectric film of the gate insulating film, the second conductive layer is the same metal material as the gate electrode, in order to provide an integrated circuit including a high-k/metal gate FET and a low resistance capacitor with improved capacitor’s electrical characteristics fabricated simultaneously (Cheng, Col. 3, lines 59-67; Col. 8, lines 9-16).
Regarding claim 2, Won in view of Cheng discloses the semiconductor device of claim 1. Further, Won discloses the semiconductor device, wherein the conductive material (e.g., 120b, the polysilicon material) (Won, Fig. 1F, ¶0070) is polysilicon, and the second insulating film (e.g., oxide film of the oxide-nitride-oxide structure) is an oxide film, but does not specifically disclose a silicon oxide film.
However, Cheng teaches forming silicon oxide/silicon nitride material layer as an interfacial layer (Cheng, Fig. 8, Col. 7, lines 37-51) before forming high-k dielectric layer.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Won/Cheng by forming oxide-nitride-oxide structure of Won including silicon oxide and silicon nitride materials as taught by Cheng, wherein the second insulating film of Won includes a silicon oxide film to have the semiconductor device, wherein the second insulating film is a silicon oxide film, in order to provide an integrated circuit including a high-k/metal gate FET and a low resistance capacitor with improved capacitor’s electrical characteristics fabricated simultaneously (Cheng, Col. 3, lines 59-67; Col. 8, lines 9-16).
Regarding claim 3, Won in view of Cheng discloses the semiconductor device of claim 1. Further, Won discloses the semiconductor device, wherein the transistor (e.g., 94) and the resistance-capacitance element (e.g., a low resistance capacitor 90) are electrically isolated from one another by an element isolation region (e.g., field oxide region 102) (Won, Fig. 1F, ¶0066) provided in the semiconductor substrate (100).
Regarding claim 7, Won in view of Cheng discloses the semiconductor device according to claim 1. Further, Won does not specifically disclose that an uppermost surface of the gate electrode and an uppermost surface of the second conductive layer are at a same height from the semiconductor substrate.
However, Cheng teaches forming a semiconductor device including a transistor and a capacitor, wherein an uppermost surface of the gate electrode (750) (Cheng, Fig. 8, Col. 7, lines 31-36; Col. 8, lines 9-16) and an uppermost surface of the second conductive layer (752) are at a same height from the semiconductor substrate (102/104/106).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Won/Cheng by forming a transistor and a capacitor including a conductive metal layer on the same substrate as taught by Cheng to have the semiconductor device, wherein an uppermost surface of the gate electrode and an uppermost surface of the second conductive layer are at a same height from the semiconductor substrate, in order to provide an integrated circuit including a high-k/metal gate FET and a low resistance capacitor with improved capacitor’s electrical characteristics fabricated simultaneously (Cheng, Col. 3, lines 59-67; Col. 8, lines 9-16).
Regarding claim 8, Won in view of Cheng discloses the semiconductor device according to claim 1. Further, Won does not specifically disclose that the dielectric film is a high-k dielectric material.
However, Cheng teaches forming a semiconductor device including a transistor and a capacitor, wherein the dielectric film (746) (Cheng, Fig. 8, Col. 7, lines 17-36) a high-k dielectric material.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Won/Cheng by forming a transistor and a capacitor including a high-k dielectric as taught by Cheng to have the semiconductor device, wherein the dielectric film is a high-k dielectric material, in order to provide an integrated circuit including a high-k/metal gate FET and a low resistance capacitor with improved capacitor’s electrical characteristics fabricated simultaneously (Cheng, Col. 3, lines 59-67; Col. 8, lines 9-16).
Regarding claim 11, Won in view of Cheng discloses the semiconductor device of claim 1. Further, Won discloses the semiconductor device, wherein the conductive material (e.g., 120b, the polysilicon material) (Won, Fig. 1F, ¶0070) is polysilicon, but does not specifically disclose that the metal material is tungsten or aluminum.
However, Cheng teaches forming the gate electrode including the metal material (Cheng, Fig. 8, Col. 7, lines 52-60) that is tungsten or aluminum.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Won/Cheng by forming the gate electrode including specific metal material as taught by Cheng to have the semiconductor device, wherein the metal material is tungsten or aluminum, in order to provide an integrated circuit including a high-k/metal gate FET and a low resistance capacitor with improved capacitor’s electrical characteristics fabricated simultaneously (Cheng, Col. 3, lines 59-67; Col. 8, lines 9-16).
Regarding claim 21, Won in view of Cheng discloses the semiconductor device of claim 1. Further, Won discloses the semiconductor device, wherein the dielectric film (e.g., 110a) (Won, Fig. 1F, ¶0070) of the gate insulating film directly contacts the upper surface of the semiconductor substrate (100).
Regarding claim 23, Won in view of Cheng discloses the semiconductor device of claim 1. Further, Won discloses the semiconductor device, wherein the second insulating film (e.g., a dielectric layer 170 including an oxide film of the oxide-nitride-oxide structure) (Won, Fig. 1F, ¶0077) is on a side surface of the third insulating film (e.g., another oxide film of the oxide-nitride-oxide structure of the dielectric layer 170).
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over US 2007/0267705 to Won in view of Cheng (US Patent No. 8,659,066) as applied to claim 1, and further in view of Park (US 2015/0357377).
Regarding claim 4, Won in view of Cheng discloses the semiconductor device according to claim 1. Further, Won discloses the semiconductor device , wherein the resistance-capacitance element further includes: a first contact plug (190a) (Won, Fig. 1F, ¶0079) electrically connected to the first conductive layer (120b), a second contact plug (190b) electrically connected to the second conductive layer (180), but does not specifically disclose, and a third contact plug electrically connected to the semiconductor substrate.
However, Park teaches forming a stacked capacitor (Park, Fig. 8, ¶0025-¶0037) having a large capacity to improve signal transfer characteristics, wherein a first power voltage terminal (V1) is applied to the second conductive layer (125/130), a second power voltage terminal (V2) is applied to the first conductive layer (115), and a third power voltage terminal (V3) is applied to the substrate bias region (140).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Won/Cheng by forming a plurality of contact plugs connected to the first conductive layer and the second conductive layer of the stacked capacitor as taught by Park to have the semiconductor device, wherein a third contact plug electrically connected to the semiconductor substrate, in order to provide a multi-stage capacitor having a large capacity to improve signal transfer characteristics (Park, ¶0007-¶0011, ¶0033, ¶0037).
Regarding claim 5, Won in view of Cheng and Park discloses the semiconductor device according to claim 4. Further, Won discloses that the first contact plug (190a) (Won, Fig. 1F, ¶0079) is connected to a portion of the upper surface of the first conductive layer (120b) not covered by the second conductive layer (198), but does not specifically disclose that a surface area of the second conductive layer is smaller than a surface area of the first conductive layer, and.
However, Park teaches forming the stacked capacitor (Park, Fig. 8, ¶0025-¶0037), wherein a surface area of the second conductive layer (125) is smaller than a surface area of the first conductive layer (115), and the second power voltage terminal (V2) is connected to a portion of the upper surface of the first conductive layer (115) not covered by the second conductive layer (125/130).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Won/Cheng/Park by forming a plurality of contact plugs connected to the first conductive layer and the second conductive layer of the stacked capacitor as taught by Park to have the semiconductor device, wherein a surface area of the second conductive layer is smaller than a surface area of the first conductive layer, , in order to provide a multi-stage capacitor having a large capacity to improve signal transfer characteristics (Park, ¶0007-¶0011, ¶0033, ¶0037).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over US 2007/0267705 to Won in view of Cheng (US Patent No. 8,659,066) and Park (US 2015/0357377) as applied to claim 4, and further in view of Ariyoshi et al. (US 2012/0034751, hereinafter Ariyoshi).
Regarding claim 6, Won in view of Cheng and Park discloses the semiconductor device according to claim 4. Further, Won does not specifically disclose that the first contact plug is in a through via hole that penetrates the second conductive layer, the second insulating film, and the third insulating film and reaches the first conductive layer.
However, Ariyoshi teaches forming an integrated circuit (Ariyoshi, Fig. 2K, ¶0015-¶0019, ¶0113-¶0115, ¶0162-¶0167, ¶0176-¶0179) comprising a flash memory cell region (I) and a capacitor region (II) including a capacitor having a first conductive layer (11a) and a second conductive layer (30a), wherein the first contact plug (58a) is in a through via hole (30c) that penetrates the second conductive layer (30a), the second insulating film (14a), and reaches the first conductive layer (11a), the first contact plug (58a) controls the potential of the lower electrode (11a) of the capacitor and the second contact plug (58b) controls the potential of the upper electrode (30a) of the capacitor, wherein the opening (30c) of the upper electrode (30a) has a reduced diameter that allows the semiconductor device to be reduced in size while maintaining the capacitance of the capacitor (Ariyoshi, Fig. 2K, ¶0002-¶0004, ¶0015-¶0019, ¶0167, ¶0179).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Won/Cheng/Park by forming an opening of the upper electrode for the contact plug as taught by Ariyoshi, wherein the opening extends through the second conductive layer and underlying insulating layer including the second insulating film and the third insulating film, and exposes the first conductive layer to have the semiconductor device, wherein the first contact plug is in a through via hole that penetrates the second conductive layer, the second insulating film, and the third insulating film and reaches the first conductive layer, in order to provide improved semiconductor device with reduced size while maintaining the capacitance of the capacitor (Ariyoshi, ¶0002-¶0004, ¶0015-¶0019, ¶0167, ¶0179).
Claim 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over US 2007/0267705 to Won in view of Cheng (US Patent No. 8,659,066) as applied to claim 1, and further in view of Chuang et al. (US 2016/0225846, hereinafter Chuang).
Regarding claim 9, Won in view of Cheng discloses the semiconductor device according to claim 1. Further, Won does not specifically disclose that the dielectric film is hafnium silicate.
However, Chuang teaches the semiconductor device, wherein the dielectric film (e.g., the logic gate dielectric 128, including high k dielectric layer 144) (Chuang, Fig. 4, ¶0018, ¶0021) is a high-k dielectric material, and includes hafnium silicate (HfSiO).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Won/Cheng by forming a high-k dielectric material including a silicate material as taught by Chuang to have the semiconductor device, wherein the dielectric film is hafnium silicate, in order to provide an improved integrated circuit comprising memory device and a capacitor compatible with high k metal gate (HKMG) technology to improve performance and reliability of the integrated circuit (Chuang, ¶0011-¶0014).
Regarding claim 10, Won in view of Cheng and Chuang discloses the semiconductor device of claim 9. Further, Won discloses the semiconductor device, wherein the conductive material (e.g., 120b, the polysilicon material) (Won, Fig. 1F, ¶0070) is polysilicon, but does not specifically disclose that the metal material is tungsten or aluminum.
However, Cheng teaches forming the gate electrode including the metal material (Cheng, Fig. 8, Col. 7, lines 52-60) that is tungsten or aluminum.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Won/Cheng/Chuang by forming the gate electrode including specific metal material as taught by Cheng to have the semiconductor device, wherein the metal material is tungsten or aluminum, in order to provide an integrated circuit including a high-k/metal gate FET and a low resistance capacitor with improved capacitor’s electrical characteristics fabricated simultaneously (Cheng, Col. 3, lines 59-67; Col. 8, lines 9-16).
Claims 12, 15-17 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0359501 to Akaiwa in view of Chuang (US 2016/0225846), Kocon (US 2013/0009225), Tsai et al. (US Patent No. 9,589,846, hereinafter Tsai), and Aloni et al. (US 2009/0239351, hereinafter Aloni).
With respect to claim 12, Akaiwa discloses a semiconductor device (e.g., an integrated circuit including low voltage transistors, high voltage transistors, and passive device including a resistor and a capacitor) (Akaiwa, Figs. 14A-14E, ¶0002, ¶0056-¶101), comprising:
a semiconductor substrate (2/4) (Akaiwa, Figs. 14A-14E, ¶0056-¶0058);
a high voltage transistor (e.g., p-type and n-type field effect transistors) (Akaiwa, Figs. 14A-14E, ¶0059, ¶0061) in a first region (500/600) of the semiconductor substrate (2/4);
a low voltage transistor (e.g., p-type and n-type field effect transistors) (Akaiwa, Figs. 14A-14E, ¶0059, ¶0061) in a second region (100/200) of the semiconductor substrate (2/4);
a very low voltage transistor (e.g., p-type and n-type field effect transistors) (Akaiwa, Figs. 14A-14E, ¶0059, ¶0061) in a third region (300/400) of the semiconductor substrate (2/4);
a passive element (e.g., a resistor and a capacitor) (Akaiwa, Figs. 14A-14E, ¶0059, ¶0061) in a fourth region (700/800) of the semiconductor substrate, the passive element (700/800) being configurable as a capacitor, and a resistor; and
an interlayer insulator (70) (Akaiwa, Figs. 14A-14E, ¶0095-¶0096) covering the high voltage transistor (500/600), the low voltage transistor (100/200), the very low voltage transistor (300/400), and the passive element (700/800), wherein
each of the said transistors (500/600, 100/200, and 300/400) includes a gate electrode (40 and 25/26) (Akaiwa, Figs. 14A-14E, ¶0090-¶0093, ¶0098-¶100), a first dielectric film (10/13 and 12) on bottom of the gate electrode (40 and 25/26),
the high voltage transistor (500/600) having a gate oxide layer (10/20L) of a first thickness (between 4 nm and 30 nm) (Akaiwa, Figs. 14A-14E, ¶0061, ¶0098-¶100) between the bottom surface of the gate electrode (40) and the semiconductor substrate (2/4), and
the low voltage transistor (100/200) (Akaiwa, Figs. 14A-14E, ¶0061, ¶0098-¶100) having a gate oxide layer (12/22L) of a second thickness (between 1.5 nm and 3 nm), less than the first thickness, between the bottom surface of the gate electrode (25/26) and the semiconductor substrate (2/4),
an upper surface of semiconductor substrate (2) in second (100/200), third (300/400), and fourth (800) regions is a same plane (e.g., as shown in Fig. 2B, the upper surface of the semiconductor substrate 2 is in a same plane in the second region 100/200, the third region 300/400, and the fourth region 800 for the devices in Fig. 14B) (Akaiwa, Figs. 14A-14E, ¶0061);
the passive element (700/800) has:
a first insulating film (12) (Akaiwa, Figs. 14A-14E, ¶0061, ¶0081, ¶0098) on the upper surface of the semiconductor substrate (2), the first insulating film (12) having the second thickness and being a same material as the gate oxide film (12) of the low voltage transistor (100/200),
Further, Akaiwa does not specifically disclose (1) a resistance-capacitance element, the resistance-capacitance element being configurable as a first-type capacitor, a second-type capacitor, and a resistor; (2) each of the said transistors includes a first high-k dielectric film on bottom and side surfaces of the gate electrode, and a first interlayer film on bottom and side surfaces of the first high-k dielectric film; (3) the resistance-capacitance element has: a first conductive layer on the first insulating film and formed of polysilicon; a stopper layer on the first conductive layer, the stopper layer being formed of insulator material; a second interlayer film on the stopper layer, the second interlayer film being formed of the same material as the first interlayer film; a second high-k dielectric film on the second interlayer film, the second high-k dielectric film being formed of the same material as the first high-k dielectric film; and a second conductive layer on the second high-k dielectric film, the second conductive layer being formed of the same material as the gate electrode, and the second high-k dielectric film and the second interlayer film are on a sidewall of the second conductive layer.
Regarding (1), Chuang discloses a semiconductor device (e.g., an integrated circuit including flash memory cell, logic devices, and a capacitor) (Chuang, Figs. 1, 4, ¶0011-¶0021, ¶0064-¶0065) comprising a capacitance element including stacked capacitors (e.g., a first capacitor C1 and a second capacitor C2) (Chuang, Figs. 1, 4, ¶0014, ¶0021) and contacts (Chuang, Figs. 1, 4, ¶0014) coupled to the top electrode (120) and the substrate (150), to provide an improved integrated circuit comprising memory device and capacitor compatible with high k metal gate (HKMG) technology to improve performance and reliability of the integrated circuit (Chuang, Figs. 1, 4, ¶0011-¶0014).
Further, Kocon teaches forming an integrated resistance-capacitance element (146/438) (Kocon, Figs. 1C, 4B, ¶0004, ¶0010, ¶0013-¶0030, ¶0046-¶0050) including a capacitor (126/426) and a resistor (142/434) by forming electrical contacts to the capacitor electrode and the doped substrate region, wherein the integrated resistance-capacitance element is formed in the active region isolated with isolation regions (e.g., trench oxide STI regions or LOCOS oxidation regions 104/404) (Kocon, Figs. 1C, 4B, ¶0013, ¶0046), and the electrical contacts are connected with the conductive layer or wiring that functions as a resistor, to provide the integrated resistance-capacitance element to control undesired voltage oscillations of the integrated circuit (Kocon, ¶0002, ¶0004, ¶0010, ¶0030, ¶0049-¶0050).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Akaiwa by forming a stacked capacitor element integrated with the memory device and having contacts coupled to the top electrode as taught by Chuang, and forming a resistor concurrently with a capacitor plate as taught by Kocon, wherein the resistor includes electrical contacts connected to the capacitor electrode of Chuang and a conductive layer or wiring that functions as a resistor to have the semiconductor device, comprising: a resistance-capacitance element, the resistance-capacitance element being configurable as a first-type capacitor, a second-type capacitor, and a resistor, in order to provide an improved integrated circuit comprising memory device and a capacitor compatible with high k metal gate (HKMG) technology to improve performance and reliability of the integrated circuit; and to provide improved integrated circuit capable of controlling the undesired voltage oscillations of the integrated circuit (Chuang, ¶0011-¶0014; Kocon, ¶0002, ¶0004, ¶0010, ¶0030, ¶0049-¶0050).
Regarding (2), Tsai teaches forming a reliable integrated circuit (Tsai, Fig. 9, Col. 1, lines 48-67; Col. 3, lines 2-67; Cols. 4-5) including a low voltage transistor (502) and a high voltage transistor (402) comprising a high-k gate dielectric layer (317) (Tsai, Fig. 9, Col. 5, lines 26-34) having U-shape on the first oxide layer (507/404) (Tsai, Fig. 9, Col. 5, lines 21-22) having different thickness, wherein each of the transistors (502 and 402) includes a first high-k dielectric film (317) on bottom and side surfaces of the gate electrode (320).
Further, Aloni teaches forming metal capacitor/gate electrode structures (Aloni, Fig. 1, ¶0005, ¶0028-¶0036) for the capacitor and high-voltage transistor, wherein the metal capacitor/gate electrode structures comprise a dielectric stack (140) including a high-k gate dielectric layer and silicon oxide layer, such that a high-k dielectric film is formed on bottom and side surfaces of the gate electrode, and a silicon oxide layer is formed on bottom and side surfaces of the first high-k dielectric film, to provide desired properties of the gate dielectric layer and capacitor dielectric layer to improve performance of the CMOS transistors and capacitor with ability to work at high voltages.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Akaiwa by forming a high-k gate dielectric layer having U-shape on the first oxide layer for the low voltage transistor and the high voltage transistor as taught by Tsai, wherein the U-shaped gate dielectric layer includes a dielectric stack of a high-k gate dielectric layer and silicon oxide layer as taught by Aloni to have the semiconductor device, wherein each of the said transistors includes a first high-k dielectric film on bottom and side surfaces of the gate electrode, and a first interlayer film on bottom and side surfaces of the first high-k dielectric film, in order to provide a reliable integrated circuit; and to provide desired properties of the gate dielectric layer and capacitor dielectric layer to improve performance of the CMOS transistors and capacitor with ability to work at high voltages (Tsai, Col. 1, lines 48-67; Aloni, ¶0005, ¶0028, ¶0036).
Regarding (3), Chuang teaches forming the capacitance element (e.g., stacked capacitors including a first capacitor C1 and a second capacitor C2) (Chuang, Fig. 4, ¶0014, ¶0021) including a first insulating film (e.g., a first capacitor dielectric 125 made of silicon oxide) (Chuang, Fig. 4, ¶0021) on the upper surface of the semiconductor substrate (102), a first conductive layer (118) on the first insulating film (125) and formed of polysilicon; a stopper layer (e.g., etch stop layer (ESL) 146) on the first conductive layer (118), the stopper layer (e.g., ESL 146) being formed of insulator material (e.g., the dielectric layer 128 made up of layers 142, 144, and 146) (Chuang, Fig. 4, ¶0018); a second interlayer film (142) on the stopper layer (e.g., on the bottom of the ESL 146), the second interlayer film (142) being formed of the same material as the first interlayer film (e.g., silicon oxide); a second high-k dielectric film (144) on the second interlayer film (142), the second high-k dielectric film (144) being formed of the same material as the first high-k dielectric film (e.g., 144, of the logic dielectric layer 128); and a second conductive layer (120) (Chuang, Fig. 4, ¶0021) on the second high-k dielectric film (144), the second conductive layer (120) being formed of the same material as the gate electrode (148).
Further, Aloni teaches forming metal capacitor/gate electrode structures (Aloni, Fig. 1, ¶0005, ¶0028-¶0036) for the capacitor and high-voltage transistor, wherein the metal capacitor/gate electrode structures comprise a dielectric stack (140) including a high-k gate dielectric layer and silicon oxide layer, such that and the second high-k dielectric film and the second interlayer film of the capacitor dielectric stack (143) are on a sidewall of the second conductive layer (157/167) of the capacitor (Aloni, Fig. 1, ¶0034), to provide desired properties of the gate dielectric layer and capacitor dielectric layer to improve performance of the CMOS transistors and capacitor with ability to work at high voltages.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Akaiwa/Chuang/Kocon/ Tsai/Aloni by forming a stacked capacitor element integrated with the memory device as taught by Chuang, forming a resistor concurrently with a capacitor plate as taught by Kocon, and forming a capacitor dielectric stack including a high-k gate dielectric layer and silicon oxide layer as taught by Aloni to have the semiconductor device, wherein the resistance-capacitance element has: a first conductive layer on the first insulating film and formed of polysilicon; a stopper layer on the first conductive layer, the stopper layer being formed of insulator material; a second interlayer film on the stopper layer, the second interlayer film being formed of the same material as the first interlayer film; a second high-k dielectric film on the second interlayer film, the second high-k dielectric film being formed of the same material as the first high-k dielectric film; and a second conductive layer on the second high-k dielectric film, the second conductive layer being formed of the same material as the gate electrode, and the second high-k dielectric film and the second interlayer film are on a sidewall of the second conductive layer, in order to provide an improved integrated circuit comprising memory device and capacitor compatible with high k metal gate (HKMG) technology to improve performance and reliability of the integrated circuit; to provide improved integrated circuit capable of controlling the undesired voltage oscillations of the integrated circuit; to provide desired properties of the gate dielectric layer and capacitor dielectric layer to improve performance of the CMOS transistors and capacitor with ability to work at high voltages (Chuang, ¶0011-¶0014; Kocon, ¶0002, ¶0004, ¶0010, ¶0030, ¶0049-¶0050; Aloni, ¶0005, ¶0028, ¶0036).
Regarding claim 15, Akaiwa in view of Chuang, Kocon, Tsai, and Aloni discloses the semiconductor device according to claim 12. Further, Akaiwa does not specifically disclose that a planar area of the second conductive layer is less than a planar area of the first conductive layer.
However, Chuang teaches forming the stacked capacitors (Chuang, Fig. 4, ¶0014, ¶0021), wherein a planar area of the second conductive layer (120) is less than a planar area of the first conductive layer (118), to provide a capacitor compatible with high k metal gate (HKMG) technology.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Akaiwa/Chuang/Kocon/ Tsai/Aloni by forming a stacked capacitor element integrated with the memory device and having contacts coupled to the top electrode as taught by Chuang to have the semiconductor device, wherein a planar area of the second conductive layer is less than a planar area of the first conductive layer, in order to provide an improved integrated circuit comprising memory device and a capacitor compatible with high k metal gate (HKMG) technology to improve performance and reliability of the integrated circuit (Chuang, ¶0011-¶0014).
Regarding claim 16, Akaiwa in view of Chuang, Kocon, Tsai, and Aloni discloses the semiconductor device according to claim 12. Further, Akaiwa discloses the semiconductor device, further comprising: a plurality of contacts (e.g., contact via structures 76A, 76G, 86A, 86G, 96A, 96G, 96R, 96C) (Akaiwa, Figs. 14A-14E, ¶0097) extending vertically in the interlayer insulator (70) to an upper surface of the interlayer insulator (70).
Regarding claim 17, Akaiwa in view of Chuang, Kocon, Tsai, and Aloni discloses the semiconductor device according to claim 12. Further, Akaiwa does not specifically disclose that an uppermost surface of each gate electrode is at a same height as an uppermost surface of the second conductive layer.
However, Chuang teaches forming the integrated circuit including flash memory cell, logic devices, and a stacked capacitor element (Chuang, Figs. 1, 4, ¶0011-¶0021, ¶0064-¶0065), wherein an uppermost surface of each gate electrode (e.g., 136/138, 120, and 148) is at a same height as an uppermost surface of the second conductive layer (120).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Akaiwa/Chuang/Kocon/ Tsai/Aloni by forming the integrated circuit including a plurality of transistors and a stacked capacitor element as taught by Chuang to have the semiconductor device, wherein an uppermost surface of each gate electrode is at a same height as an uppermost surface of the second conductive layer, in order to provide an improved integrated circuit comprising memory device and a capacitor compatible with high k metal gate (HKMG) technology to improve performance and reliability of the integrated circuit (Chuang, ¶0011-¶0014).
Regarding claim 22, Akaiwa in view of Chuang, Kocon, Tsai, and Aloni discloses the semiconductor device according to claim 12. Further, Akaiwa discloses the semiconductor device, wherein the upper surface of the semiconductor substrate (2) (Akaiwa, Figs. 14B, ¶0094-¶0101) in the first region (500/600) is in a different plane (e.g., the upper surface of the substrate 2 is lower in the first region 500/600 than that in the second to fourth regions) from that of the upper surface of the semiconductor substrate (2) in second (100/200), third (300/400), and fourth (800) regions.
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
In response to Applicant’s argument that “Akaiwa fails to "disclose that the second high-k dielectric film and the second interlayer film are on a sidewall of the second conductive layer", the examiner submits that newly discovered prior art by Aloni teaches forming metal capacitor/gate electrode structures comprising a dielectric stack (140) (Aloni, Fig. 1, ¶0028) including a high-k gate dielectric layer and silicon oxide layer, such that and the second high-k dielectric film and the second interlayer film of the capacitor dielectric stack (143) are on a sidewall of the second conductive layer (157/167) of the capacitor (Aloni, Fig. 1, ¶0034).
Thus, the above Applicant’s argument is not persuasive, and the rejection of claim 12 under U.S.C. § 103 over Akaiwa in view of Chuang, Kocon, Tsai, and Aloni is maintained.
Regarding dependent claims 2-11, 15-17, and 21-23 which depend on the independent claims 1 and 12, the examiner respectfully submits that the applicant’s arguments with respect to dependent claims are not persuasive for the above reasons, thus, the rejections of the dependent claims are sustained.
Conclusion
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/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891
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