Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-19 of U.S. Patent No. 12,235,775 in view of Anthony (US 4,885,680) and/or Bradbury (US 2017/0220475). Any portions of the claims not explicitly taught by Patent No. 12,235,775 are taught and/or made obvious by Anthony and/or Bradbury as described in the rejection below. As the patent and the prior art are all associated with data caching, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to have been able to use the prior art to modify the claimed language of Patent No. 12,235,755.
Please note that MPEP § 804 states:
“A complete response to a nonstatutory double patenting (NSDP) rejection is either a reply by applicant showing that the claims subject to the rejection are patentably distinct from the reference claims or the filing of a terminal disclaimer in accordance with 37 CFR 1.321 in the pending application(s) with a reply to the Office action (see MPEP § 1490 for a discussion of terminal disclaimers). Such a response is required even when the nonstatutory double patenting rejection is provisional. As filing a terminal disclaimer, or filing a showing that the claims subject to the rejection are patentably distinct from the reference application’s claims, is necessary for further consideration of the rejection of the claims, such a filing should not be held in abeyance. Only objections or requirements as to form not necessary for further consideration of the claims may be held in abeyance until allowable subject matter is indicated. Replies with an omission should be treated as provided in MPEP § 714.03. “
In accordance with MPEP § 804 and §714.03 the examiner will hold any response/amendments to this office action as NON-COMPLIANT without any additional extensions of time that do not contain one of:
An approved Terminal Disclaimer, OR
A Showing that the claims subject to the rejection are patentably distinct from the reference claims.
In regards to b.) The showing must be made against the claims subject to the rejection (not amended claims), as such the claims as they were originally written and rejected. A showing against amended claims is NOT proper, as the original claims have already been examined (i.e. elected by original presentation, see MPEP §821.03), and presenting all amended claims directed to another patently distinct invention will result in the claims not being entered and being the response designated as nonresponsive. A proper showing or a filing of a terminal disclaimer is required for further consideration of the rejection of the claims. Depending on the claims that have been filed and rejected under NSDP, it may be practically impossible for any arguments and/or evidence to be capable of providing a proper showing that the claims as filed are patentably distinct. In this case, the applicant should file the terminal disclaimer, as it is required for a complete response to this action, and further consideration of the application.
As show below, the filing of a Terminal Disclaimer is not an admission, creates no issues of estoppel, and can be petitioned to be removed once the claims are in condition for allowance and the applicant believes (and can show) the allowable claims are now patentably distinct from the original reference claims.
“The filing of a terminal disclaimer to obviate a rejection based on nonstatutory double patenting is not an admission of the propriety of the rejection. Quad Environmental Technologies Corp. v. Union Sanitary District, 946 F.2d 870, 20 USPQ2d 1392 (Fed. Cir. 1991). In Quad Environmental Technologies, the court indicated that the "filing of a terminal disclaimer simply serves the statutory function of removing the rejection of double patenting, and raises neither a presumption nor estoppel on the merits of the rejection." “(MPEP § 804.02).
“If a terminal disclaimer is filed in an application in which the claims are then canceled or otherwise shown to be patentably distinct from the reference claims, the terminal disclaimer may be withdrawn before issuance of the patent by filing a petition under 37 CFR 1.182 requesting withdrawal of the recorded terminal disclaimer. A terminal disclaimer may not be withdrawn after issuance of the patent. See MPEP § 1490, subsection VIII, for a complete discussion of withdrawal of a terminal disclaimer.” (MPEP § 804.02).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2, 7, 10, 14, 16 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In regards to claims 2, 10, and 16, The limitation “read intensive utilities that are likely to read tracks, in the cache at the storage system, only once” (bolded for emphasis) contain the terms “read intensive” and “likely” which are relative terms which renders the claim indefinite. The terms are not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. For purposes of examination, it will be determined that any program or part of data associated with a program can be considered a “read intensive utility”.
In regards to claims 7, 14, and 20, the claim states “the high latency path can be processed when there is a cache hit and a cache miss at the cache in the storage system”, it’s not clear how both a cache hit and a cache miss is possible for a request, as they are mutually exclusive from one another, either the data is in the cache (i.e. a hit) or the data is not in the cache (i.e. a miss). For purposes of examination it will be interpreted as a “cache hit or a cache miss”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Anthony (US 4,885,680) in view of Bradbury (US 2017/0220475).
In regards to claim 1, 9, and 15, taking claim 9 as exemplary, Anthony teaches
generating a track access request for a track in the storage system; (C11:55-C12:17 and fig. 9, an access request is sent to the MMU for a set of data)
determining whether the track access request is for a designated utility; (C10:29-C11:17 and fig. 5-7 teaches that pages can have an associated “cacheability” bit and a marked data bit (MDB), the MDB is used to show that the data should only be temporarily cacheable (i.e. the track request is associated with a “designated utility” that is likely to only temporarily need the data cached). The cacheability attributes of each set of data associated a program can be determined during compilation of the program, and stored in a table and referenced by the operating system. C12:49-66 teaches that the MDB can also be multiple bits so that multiple different levels or classes of volatility can be set for the transient cache data.)
submitting the track access request with a demotion hint to cause the track to be indicated on a transient cache list in response to determining that the track access request is for the designated utility; (C11:18-27 and fig. 8 teaches that the MDB (i.e. demotion hint) is stored with the cache line and that if set indicates that the cache line is temporarily cacheable and transitory (i.e. all cache lines marked as such are “indicated” to be on a transient cache list)
submitting the track access request without a demotion hint in response to determining that the track access request is not for the designated utility to cause the track to be indicated on a prolonged cache list, (C11:18-27 and fig. 8 teaches that the MDB (i.e. demotion hint) is stored with the cache line and that if set indicates that the cache line is temporarily cacheable and transitory, therefore if the MDB isn’t set, then the cache line is NOT considered temporary, and as such are “indicated” to be on a prolonged cache list)
Anthony may not explicitly teach
A system for submitting track access requests to a storage system managing tracks in a storage in a cache, comprising: a processor; and a computer readable storage medium having computer readable program code embodied therein that when executed performs operations, the operations comprising
wherein demotion of tracks is first attempted from the transient cache list before demoting tracks from the prolonged cache list.
Anthony does teach in C6:9-10 that a least recently used algorothim can be used, but doesn’t provide distinguishing between cache lines marked with a MDB or not.
However, Bradbury in ¶111 teaches that transient data (in a cache) can be treated differently than non-transient data and that transient data can mark transient data as least recently used, such that it will be displaced (i.e. evicted/demoted) prior to non-transient data. ¶132 also teaches “The present invention may be a system, a method, and/or a computer program product. The computer program product may include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present invention.”
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to have incorporated the teachings of Bradbury to improve the system of Anthony such that cache lines determined and marked as being associated with a transitory nature (i.e. a designated utility) can be marked as LRU in the cache so that they will be evicted prior to cache lines containing data not marked as transitory. The motivation for such modification is that this prevents transitory data from taking precedence over more permanent data in the cache that has a much higher likelihood of being reused, increasing the effectiveness of the cache system.
In regards to claims 2, 10 and 16, Anthony further teaches
wherein designated utilities comprise read intensive utilities that are likely to read tracks, in the cache at the storage system, only once. (C10:29-C11:17 and fig. 5-7 teaches that pages can have an associated “cacheability” bit and a marked data bit (MDB), the MDB is used to show that the data should only be temporarily cacheable (i.e. the track request is associated with a “designated utility” that is likely to only temporarily need the data cached). The cacheability attributes of each set of data associated a program can be determined during compilation of the program, and stored in a table and referenced by the operating system.)
In regards to claims 3, 11 and 17, Anthony further teaches and/or makes obvious
wherein the demotion hint comprises one of an accelerated demotion and an immediate demotion, wherein the immediate demotion causes demoting the track from the cache after returning the track to the track access request comprising a read request. (C12:49-66 teaches that the MDB can also be multiple bits so that multiple different levels or classes of volatility can be set for the transient cache data. (i.e. an “immediate demotion” level, and an “accelerated demotion” level can be set). C1:54-57 teaches that identified read/writes can invalidate the data in the cache after it has been returned to the processor). It should be noted that C1:54-57 is part of the discussion of prior art, however, C12:34-40 states “Many modifications of the cache architecture could be made to those skilled in the art such as features set forth in the prior art section while still essentially incorporating the herein disclosed invention” as such, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to have incorporated this modification such that the cache line data can immediately be invalidated in the cache once it is used by the processor. The motivation for such is that this keeps the cache “clean” and also doesn’t require the processor to issue an additional invalidation request, increasing the efficiency of the cache system.
In regards to claim 4 Anthony further teaches and/or makes obvious
wherein the immediate demotion causes the demoting the storage system to demote the track after returning the track to the track access request when the track was not in the cache when the storage system received the track access request. (in addition to what was stated above for claim 3, C11:64-C12:2 further teaches that if the track was not in the cache (i.e. a cache miss occurs), then the data will be loaded into the cache from memory)
In regards to claims 5, 12 and 18, Anthony further teaches and/or makes obvious
wherein accelerated demotion is indicated for utilities submitting read requests when there is a higher likelihood that there will be a subsequent read to the track than read requests from utilities for which the immediate demotion is indicated. (C12:49-66 teaches that the MDB can also be multiple bits so that multiple different levels or classes of volatility can be set for the transient cache data. (i.e. an “immediate demotion” level for the highest volatility level/class, and an “accelerated demotion” level can be set for a relatively lower volatility level/class of data).)
In regards to claims 6, 13 and 19, Anthony further teaches and/or makes obvious
wherein the demotion hint causes the storage system to indicate the track on the transient cache list to demote if a demotion criteria with respect to the transient cache list is satisfied before demoting tracks from the prolonged cache list. (C12:49-66 teaches that the MDB can also be multiple bits so that multiple different levels or classes of volatility can be set for the transient cache data, and that an instruction can be defined (i.e. a demotion criteria is set/satisfied) that invalidates (i.e. demotes) all entries of a certain level/class)
In regards to claims 7, 14 and 20, Anthony further teaches and/or makes obvious
wherein track access requests are sent down one of a high latency path and a low latency path, wherein the demotion hint is designated for utilities submitting tracks on the high latency path, wherein track access requests for the low latency path require a cache hit to complete, and wherein track access requests on the high latency path can be processed when there is a cache hit and a cache miss at the cache in the storage system. (C6:13-17 teaches that if the data is not in the cache, then the request is a miss and the data must be brought into the cache. C11:11-27 teaches the MDB (demotion hint) is added to the cache line when it is brought into the cache (i.e. during a cache miss). The latency of a cache hit is a “low latency” path as compared to a cache miss “a high latency path”.
In regards to claim 8, Anthony further teaches and/or makes obvious
wherein track access requests are sent on the low latency path for tracks previously requested without a demotion hint and indicated on the prolonged cache list. (C6:13-17 teaches that if the data is not in the cache, then the request is a miss and the data must be brought into the cache. i.e. data is either in the cache (hit, low latency) or not (miss, high latency). Tracks not marked as volatile (i.e. without a demotion hint) and in the cache (i.e. on the cache list) will be a hit and therefore use the “low latency path”.)
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Gupta (US 2021/0255965) teaches that cache lines can be marked to include a maximum amount of time that they should be retained in the cache (i.e. indicating certain transitory/volatile cache lines)
Sadasivam (US 2018/0129629) teaches the use of a hint cache to assist in determining caching/evicting/promotion of cache lines.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON W BLUST whose telephone number is (571)272-6302. The examiner can normally be reached 12-8:30 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain Alam can be reached at (571) 272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JASON W BLUST/ Primary Examiner, Art Unit 2132