Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy of Application No. KR10-2022-0078345, filed on June 27, 2022, has been received.
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed July 23, 2026. Claims 1, 13, and 20 are amended. Claim 19 is cancelled. Claim 21 is newly added. The Examiner notes that claims 1-18 and 20-21 are examined.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-12 are rejected under 35 U.S.C. 103 as being unpatentable over Sakakibara (US 10,916,556 B1) in view of Yamasaka (US 2019/0296041 A1).
With respect to claim 1, Sakakibara teaches in Figs. 1, 24B, and 27A-B:
A three-dimensional semiconductor memory device (abstract “three-dimensional memory device) comprising:
a first substrate (semiconductor substrate 8);
a peripheral circuit structure on the first substrate (CMOS circuitry 710); and
a cell array structure (memory array region 100, seen in Fig. 27B) on the peripheral circuit structure, wherein the cell array structure includes a stacked structure (stack including 132, 146, 170, 232, and 246) including gate electrodes (electrically conductive layers 146 and 246) extending in a first direction, a source structure on the stacked structure (source select level conductive layer 118 and source contact semiconductor layer 114B), and a second substrate (source contact semiconductor layer 114A) in contact with the source structure (114A in contact with 114B),
wherein the source structure includes a first source conductive pattern (118) between the second substrate (114A) and the stacked structure, and a second source conductive pattern (114B) on the first source conductive pattern (118),
wherein the second source conductive pattern (114B) includes a first source part between the first source conductive pattern (118) and the second substrate (114A),
a source connection part passing through the second substrate and extending in the first direction, and a second source part on the second substrate and connected to the first source part through the source connection part (see annotated Fig. 24B above),
wherein the source connection part is continuous with the first source part (both are formed continuously as a part of 114B),
wherein the first source conductive pattern (118) contacts the first source part (see annotated Fig. 24B) (elements are at least in indirect physical contact through layers 117, 116, and 331 and in electrical contact through 60)
Sakakibara fails to teach:
wherein the stacked structure is between the peripheral circuit structure and the source structure.
Yamasaka teaches:
wherein the stacked structure (insulative layers 45 and conductive layers 13-22) is between the peripheral circuit structure (circuitry chip 200) and the source structure (source line 11, insulation layer 47, conductive layer 48, insulation layer 49).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Sakakibara with the teaching of Yamasaka so that the stacked structure is between the peripheral circuit structure and the source structure, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
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With respect to claim 2, Sakakibara further teaches:
wherein the cell array structure further includes vertical channel structures (vertical semiconductor channel 60) connected to the source structure (114B and 118) through the stacked structure (channel extends through the stacked structure), the vertical channel structures including vertical semiconductor patterns (“vertical semiconductor channel”),
wherein upper portions of the vertical channel structures are inserted into a lower portion of the second substrate (channel 60 extends through 114A, upper and lower are relative terms that depend on orientation of the device and do not hold patentable weight), and
wherein the vertical semiconductor patterns (60) of the vertical channel structures are electrically connected to the first source part (118).
With respect to claim 3, Sakakibara further teaches:
wherein a thickness of the second source part (see annotated Fig. 24B above) is greater than a thickness of the second substrate (114A) (the thicknesses of each element are variable, Fig. 24B shows that at least at the thinnest portion of 114A has a lower thickness than the thickest portion of the second source part).
With respect to claim 4, Sakakibara further teaches:
wherein a thickness of the second source part is greater than a thickness of the first source part (the thicknesses are variable in the lateral direction, Fig. 25 shows that the thickest portion of the second source part has a greater thickness than the thinnest portion of the first source part).
With respect to claim 5, Sakakibara further teaches:
wherein the stacked structure includes a first stacked structure (portion to the right of dielectric trench fill structure 76 in Fig. 27A) and a second stacked structure (portion to the left of dielectric trench fill structure 76 in Fig. 27A),
wherein the cell array structure further includes a separation pattern (dielectric trench fill structure 76 and U-shaped semiconductor oxide 122) between the first stacked structure and the second stacked structure and extending in the first direction,
and wherein the source connection part has a line shape substantially parallel to the separation pattern (both are vertical extending in the direction of the stack).
With respect to claim 6, Sakakibara further teaches:
wherein the source connection part comprises a first source connection part on the first stacked structure and a second source connection part on the second stacked structure (see annotated Fig. 27A above).
With respect to claim 7, Sakakibara further teaches:
wherein the first source part includes a first stacked structure source part between the first source connection part and the first stacked structure, and a second stacked structure source part between the second source connection part and the second stacked structure, and
wherein the first stacked structure source part and the second stacked structure source part are spaced apart from each other in a second direction intersecting the first direction with the separation pattern therebetween (see annotated Fig. 27A, first and second stacked structure source parts are separated by 122).
With respect to claim 8, Sakakibara further teaches:
wherein the second source part is electrically connected to the first stacked structure source part and the second stacked structure source part (see annotated Figs. 24B and 27A above, second source part is connected to the first stacked structure source part through the first source connection part and the second stacked structure source part through the second source connection part).
With respect to claim 9, Sakakibara further teaches:
wherein the cell array structure further includes vertical channel structures (vertical semiconductor channel 60) connected to the source structure (114B and 118) through the stacked structure (channel extends through the stacked structure), the vertical channel structures including vertical semiconductor patterns (“vertical semiconductor channel”),
and wherein the source connection part (see annotated Figs. 24B and 27A above) is between the separation pattern (122 and 76) and a vertical channel structure (60) that is closest to the separation pattern among the vertical channel structures (see Fig. 27A).
With respect to claim 10, Sakakibara further teaches:
wherein, in a plan view, the source connection part overlaps at least a portion of the separation pattern (source connection part overlaps at least a portion of the 122 in a lateral direction).
With respect to claim 11, Sakakibara further teaches:
wherein the first source part, the source connection part, and the second source part include a same material (all parts are formed continuously as a part of 114A).
With respect to claim 12, Sakakibara further teaches:
wherein the cell array structure includes a cell array region (100) and a cell array contact region (staircase region 300) on one side of the cell array region,
and wherein the source connection part is within the cell array region (see Fig. 17B, source connection part is within both regions 100 and 300)
Response to Arguments
Applicant's arguments filed July 23, 2026, with respect to claim 1 have been fully considered but they are not persuasive. Applicant argues that the device of Sakakibara does not teach the amended claim limitations. The Examiner notes that under a broadest reasonable interpretation “contacts” can refer to indirect or direct physical, electrical, or thermal contact and therefore the claimed elements contact each other under a broadest reasonable interpretation of the claim language.
Applicant’s arguments, see page 8-12, filed July 23, 2026, with respect to claims 13 and 20 have been fully considered and are persuasive. The prior art rejections of claims 13, 20, and their dependents have been withdrawn.
Allowable Subject Matter
Claims 13-18 and 20-21 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 13, prior art of record does not fairly disclose or make obvious the claimed device as a whole. Specifically, the closest prior art (which has been made of record) fail to disclose (by themselves or in combination) the limitations of “wherein the source structure includes a first source conductive pattern between the second substrate and the stacked structure, and a second source conductive pattern on the first source conductive pattern, wherein the second source conductive pattern includes a first source part between the first source conductive pattern and the second substrate, a source connection part passing through the semiconductor layer of the second substrate, and a second source part on the second substrate and connected to the first source part through the source connection part, wherein the cell array structure further includes a separation pattern between the first stacked structure and the second stacked structure, with the cell array structure extending in the first direction, and wherein the source connection part is between the separation pattern and a first vertical channel structure closest to the separation pattern among the vertical channel structures with a portion of the second substrate between the source connection part and the first vertical channel structure” of claim 13 in combination with the additionally claimed features, as are claimed by the Applicant. Thus, the Applicant’s claims are determined to be novel and non-obvious. The prior art of record, Sakakibara (US 10,916,556 B1) does not teach the newly amended limitations of claim 13 because the element identified as the “source connection part” directly abuts the vertical channel structure and is located between the vertical channel structure and the second substrate.
Dependent claims 14-18 are allowed at least for the same reason as independent claim 13 upon which they depend.
Regarding claim 20, prior art of record does not fairly disclose or make obvious the claimed device as a whole. Specifically, the closest prior art (which has been made of record) fail to disclose (by themselves or in combination) the limitations of “ a vertical channel structure connected to the source structure through the stacked structure, and a second substrate in contact with the source structure, wherein the source structure includes a first source conductive pattern between the second substrate and the stacked structure, and a second source conductive pattern on the first source conductive pattern, wherein the second source conductive pattern includes a first source part between the first source conductive pattern and the second substrate, a source connection part passing through the second substrate and extending in the first direction, and a second source part on the second substrate and connected to the first source part through the source connection part, wherein the vertical channel structure includes a semiconductor pattern, and wherein the second substrate and the semiconductor pattern are spaced apart from each other in a vertical direction” of claim 20 in combination with the additionally claimed features, as are claimed by the Applicant. Thus, the Applicant’s claims are determined to be novel and non-obvious. The prior art of record, Sakakibara (US 10,916,556 B1) does not teach the newly amended limitations of claim 20 because the element identified as the second substrate is formed at the same level as a portion of the semiconductor pattern of the vertical channel structure and is therefore not spaced apart from it in the vertical direction.
Dependent claims 21 is allowed at least for the same reason as independent claim 20 upon which it depends.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/A.M.W./Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
