Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on January 7, 2026 has been entered.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy of Application No. KR10-2022-0078345, filed on June 27, 2022 has been received.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on February 13, 2026 is being considered by the examiner.
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed January 7, 2026. Claims 1, 13, and 20 are amended. The Examiner notes that claims 1-20 are examined.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 13-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sakakibara (US 10,916,556 B1).
With respect to claim 13, Sakakibara teaches in Figs. 1, 24B, and 27A:
A three-dimensional semiconductor memory device (abstract “three-dimensional memory device) comprising:
a first substrate (semiconductor substrate 8);
a peripheral circuit structure on the first substrate (CMOS circuitry 710); and
a cell array structure (memory array region 100, seen in Fig. 27B) on the peripheral circuit structure, wherein the cell array structure includes a stacked structure (stack including 132, 146, 170, 232, and 246) including conductive patterns (electrically conductive layers 146 and 246) extending in a first direction, a source structure on the stacked structure (source select level conductive layer 118 and source contact semiconductor layer 114B), vertical channel structures (vertical semiconductor channels 60) connected to the source structure through the stacked structure, and a second substrate (source contact semiconductor layer 114A) in contact with the source structure (114A in contact with 114B), the second substrate including a semiconductor layer (semiconductor layer 114A)
wherein the source structure includes a first source conductive pattern (118) between the second substrate (114A) and the stacked structure, and a second source conductive pattern (114B) on the first source conductive pattern (118),
wherein the second source conductive pattern (114B) includes a first source part between the first source conductive pattern (118) and the second substrate (114A),
a source connection part passing through the semiconductor layer of the second substrate, and a second source part on the second substrate and connected to the first source part through the source connection part (see annotated Fig. 24B below),
wherein the stacked structure includes a first stacked structure (portion to the right of dielectric trench fill structure 76 in Fig. 27A) and a second stacked structure (portion to the left of dielectric trench fill structure 76 in Fig. 27A),
wherein the cell array structure further includes a separation pattern (dielectric trench fill structure 76 and U-shaped semiconductor oxide 122) between the first stacked structure and the second stacked structure and extending in the first direction, with the cell array structure extending in the first direction (vertical direction),
and wherein the source connection part (see annotated Figs. 24B and 27A below) is between the separation pattern (122 and 76) and a vertical channel structure (60) that is closest to the separation pattern among the vertical channel structures (see Fig. 27A).
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With respect to claim 14, Sakakibara further teaches:
wherein the source connection part (see annotated Fig. 24B above) is in a slit (hole in substrate that includes channel string and source connection part) passing through the second substrate (114A) and extending in the first direction (vertical direction)
With respect to claim 15, Sakakibara further teaches:
wherein a thickness of the second source part is greater than a thickness of the first source part (the thicknesses are variable in the lateral direction, Fig. 25 shows that the thickest portion of the second source part has a greater thickness than the thinnest portion of the first source part).
wherein a thickness of the second source part (see annotated Fig. 24B above) is greater than a thickness of the second substrate (114A) (the thicknesses of each element are variable, Fig. 24B shows that at least at the thinnest portion of 114A has a lower thickness than the thickest portion of the second source part).
With respect to claim 16, Sakakibara further teaches:
wherein the source connection part has a linear shape substantially parallel to the separation pattern (both are vertical extending in the direction of the stack).
With respect to claim 17, Sakakibara further teaches:
wherein the source connection part (see annotated Fig. 24B) above is on each of the first stacked structure and the second stacked structure (see annotated Fig. 27A above)
With respect to claim 18, Sakakibara further teaches:
wherein the source connection part comprises a first source connection part on the first stacked structure and a second source connection part on the second stacked structure (see annotated Fig. 27A above).
wherein the first source part includes a first stacked structure source part between the first source connection part and the first stacked structure, and a second stacked structure source part between the second source connection part and the second stacked structure, and
wherein the first stacked structure source part and the second stacked structure source part are spaced apart from each other in a second direction intersecting the first direction with the separation pattern therebetween (see annotated Fig. 27A, first and second stacked structure source parts are separated by 122).
With respect to claim 19, Sakakibara further teaches:
wherein the second source part is electrically connected to the first stacked structure source part and the second stacked structure source part (see annotated Figs. 24B and 27A above, second source part is connected to the first stacked structure source part through the first source connection part and the second stacked structure source part through the second source connection part).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-12 are rejected under 35 U.S.C. 103 as being unpatentable over Sakakibara (US 10,916,556 B1) in view of Yamasaka (US 2019/0296041 A1).
With respect to claim 1, Sakakibara teaches in Figs. 1, 24B, and 27A-B:
A three-dimensional semiconductor memory device (abstract “three-dimensional memory device) comprising:
a first substrate (semiconductor substrate 8);
a peripheral circuit structure on the first substrate (CMOS circuitry 710); and
a cell array structure (memory array region 100, seen in Fig. 27B) on the peripheral circuit structure, wherein the cell array structure includes a stacked structure (stack including 132, 146, 170, 232, and 246) including gate electrodes (electrically conductive layers 146 and 246) extending in a first direction, a source structure on the stacked structure (source select level conductive layer 118 and source contact semiconductor layer 114B), and a second substrate (source contact semiconductor layer 114A) in contact with the source structure (114A in contact with 114B),
wherein the source structure includes a first source conductive pattern (118) between the second substrate (114A) and the stacked structure, and a second source conductive pattern (114B) on the first source conductive pattern (118),
wherein the second source conductive pattern (114B) includes a first source part between the first source conductive pattern (118) and the second substrate (114A),
a source connection part passing through the second substrate and extending in the first direction, and a second source part on the second substrate and connected to the first source part through the source connection part (see annotated Fig. 24B above),
wherein the source connection part is continuous with the first source part (both are formed continuously as a part of 114B), and
Sakakibara fails to teach:
wherein the stacked structure is between the peripheral circuit structure and the source structure.
Yamasaka teaches:
wherein the stacked structure (insulative layers 45 and conductive layers 13-22) is between the peripheral circuit structure (circuitry chip 200) and the source structure (source line 11, insulation layer 47, conductive layer 48, insulation layer 49).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Sakakibara with the teaching of Yamasaka so that the stacked structure is between the peripheral circuit structure and the source structure, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
With respect to claim 2, Sakakibara further teaches:
wherein the cell array structure further includes vertical channel structures (vertical semiconductor channel 60) connected to the source structure (114B and 118) through the stacked structure (channel extends through the stacked structure), the vertical channel structures including vertical semiconductor patterns (“vertical semiconductor channel”),
wherein upper portions of the vertical channel structures are inserted into a lower portion of the second substrate (channel 60 extends through 114A, upper and lower are relative terms that depend on orientation of the device and do not hold patentable weight), and
wherein the vertical semiconductor patterns (60) of the vertical channel structures are electrically connected to the first source part (118).
With respect to claim 3, Sakakibara further teaches:
wherein a thickness of the second source part (see annotated Fig. 24B above) is greater than a thickness of the second substrate (114A) (the thicknesses of each element are variable, Fig. 24B shows that at least at the thinnest portion of 114A has a lower thickness than the thickest portion of the second source part).
With respect to claim 4, Sakakibara further teaches:
wherein a thickness of the second source part is greater than a thickness of the first source part (the thicknesses are variable in the lateral direction, Fig. 25 shows that the thickest portion of the second source part has a greater thickness than the thinnest portion of the first source part).
With respect to claim 5, Sakakibara further teaches:
wherein the stacked structure includes a first stacked structure (portion to the right of dielectric trench fill structure 76 in Fig. 27A) and a second stacked structure (portion to the left of dielectric trench fill structure 76 in Fig. 27A),
wherein the cell array structure further includes a separation pattern (dielectric trench fill structure 76 and U-shaped semiconductor oxide 122) between the first stacked structure and the second stacked structure and extending in the first direction,
and wherein the source connection part has a line shape substantially parallel to the separation pattern (both are vertical extending in the direction of the stack).
With respect to claim 6, Sakakibara further teaches:
wherein the source connection part comprises a first source connection part on the first stacked structure and a second source connection part on the second stacked structure (see annotated Fig. 27A above).
With respect to claim 7, Sakakibara further teaches:
wherein the first source part includes a first stacked structure source part between the first source connection part and the first stacked structure, and a second stacked structure source part between the second source connection part and the second stacked structure, and
wherein the first stacked structure source part and the second stacked structure source part are spaced apart from each other in a second direction intersecting the first direction with the separation pattern therebetween (see annotated Fig. 27A, first and second stacked structure source parts are separated by 122).
With respect to claim 8, Sakakibara further teaches:
wherein the second source part is electrically connected to the first stacked structure source part and the second stacked structure source part (see annotated Figs. 24B and 27A above, second source part is connected to the first stacked structure source part through the first source connection part and the second stacked structure source part through the second source connection part).
With respect to claim 9, Sakakibara further teaches:
wherein the cell array structure further includes vertical channel structures (vertical semiconductor channel 60) connected to the source structure (114B and 118) through the stacked structure (channel extends through the stacked structure), the vertical channel structures including vertical semiconductor patterns (“vertical semiconductor channel”),
and wherein the source connection part (see annotated Figs. 24B and 27A above) is between the separation pattern (122 and 76) and a vertical channel structure (60) that is closest to the separation pattern among the vertical channel structures (see Fig. 27A).
With respect to claim 10, Sakakibara further teaches:
wherein, in a plan view, the source connection part overlaps at least a portion of the separation pattern (source connection part overlaps at least a portion of the 122 in a lateral direction).
With respect to claim 11, Sakakibara further teaches:
wherein the first source part, the source connection part, and the second source part include a same material (all parts are formed continuously as a part of 114A).
With respect to claim 12, Sakakibara further teaches:
wherein the cell array structure includes a cell array region (100) and a cell array contact region (staircase region 300) on one side of the cell array region,
and wherein the source connection part is within the cell array region (see Fig. 17B, source connection part is within both regions 100 and 300)
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Sakakibara (US 10,916,556 B1) in view of Yamasaka (US 2019/0296041 A1) and Jeon (US 2020/0365213 A1).
With respect to claim 20, Sakakibara teaches:
A three-dimensional semiconductor memory device (abstract “three-dimensional memory device) comprising:
a first substrate (semiconductor substrate 8);
a peripheral circuit structure on the first substrate (CMOS circuitry 710); and
a cell array structure (memory array region 100 and staircase region 300, seen in Fig. 27B) on the peripheral circuit structure
with the cell array structure including a cell array region (100) and a cell array contact region (300),
wherein the cell array structure includes a stacked structure including gate electrodes (electrically conductive layers 146 and 246) extending in a first direction, a source structure on the stacked structure (source select level conductive layer 118 and source contact semiconductor layer 114B), and a second substrate (source contact semiconductor layer 114A) in contact with the source structure (114A in contact with 114B),
wherein the source structure includes a first source conductive pattern (118) between the second substrate (114A) and the stacked structure, and a second source conductive pattern (114B) on the first source conductive pattern (118),
wherein the second source conductive pattern (114B) includes a first source part between the first source conductive pattern (118) and the second substrate (114A),
a source connection part passing through the second substrate and extending in the first direction, and a second source part on the second substrate and connected to the first source part through the source connection part (see annotated Fig. 24B above),
Sakakibara does not specify the impurity concentration of layer 118 and does not explicitly teach:
wherein the source connection part has an impurity concentration that is different from the first source conductive pattern,
However, Sakakibara teaches that both the source connection part (portion of 114B) and the first source conductive pattern (118) may be made from silicon doped with impurities. The ordinary artisan would understand that changing the impurity concentration of doped silicon changes the conductive properties of the material. “Generally, differences in concentration or temperature will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such concentration or temperature is critical. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)” MPEP 2144.05(II)(A). It would have been obvious for the ordinary artisan to adjust the impurity concentrations of the materials in Sakakibara such that the source connection part and source conductive patterns have different impurity concentrations. The ordinary artisan would be motivated to make such a modification to optimize the conductivity of the semiconductor layers through routine experimentation to find the optimal working conditions for the semiconductor device.
Sakakibara fails to teach:
wherein the stacked structure is between the peripheral circuit structure and the source structure;
a controller electrically connected to the three-dimensional semiconductor memory device through an input/output pad, wherein the controller is configured to control the three-dimensional semiconductor memory device.
Yamasaka teaches:
wherein the stacked structure (insulative layers 45 and conductive layers 13-22) is between the peripheral circuit structure (circuitry chip 200) and the source structure (source line 11, insulation layer 47, conductive layer 48, insulation layer 49).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Sakakibara with the teaching of Yamasaka so that the stacked structure is between the peripheral circuit structure and the source structure, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Jeon teaches:
and a controller (memory controller 300) electrically connected to the three-dimensional semiconductor memory device (memory device 500) through an input/output pad (input-output pads and/or 4205 or 4305),
wherein the controller is configured to control the three- dimensional semiconductor memory device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Jeon into the device of Sakakibara/Yamasaka to include a memory controller coupled to the 3D memory device through input/output pads. The ordinary artisan would have been motivated to modify Sakakibara/Yamasaka in the manner set forth above for the purpose of performing read, write, and erase operation (para. 28 of Jeon).
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON MICHAEL WEGNER whose telephone number is (571)270-7647. The examiner can normally be reached Mon-Fri 8:30 AM - 5 PM.
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/A.M.W./ Examiner, Art Unit 2897
/JACOB Y CHOI/ Supervisory Patent Examiner, Art Unit 2897
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