Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Amendment filed on 2/26/2026 has been entered. Claim 1 is amended. Claims 16 – 23, 25, 27 are canceled. Claims 24, 26, 28 – 30 are withdrawn. Claims 1 – 15 remain pending in the application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 5, 9 – 15 are rejected under 35 U.S.C. 103 as being unpatentable over Yang (Pub. No. US 20200411509 A1), hereinafter Yang, in view of Son (Pub. No. 20190326316 A1), hereinafter Son.
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Regarding Independent Claim 1 (Currently Amended), Yang teaches a semiconductor memory device comprising:
a semiconductor layer ( Yang, FIG. 3, 348; [0052], semiconductor layer 348 ) including a first face ( Yang, FIG. 3, bottom surface of 348 ) and a second face ( Yang, FIG. 3, top surface of 348 ) opposite to the first face in a first direction ( Yang, FIG. 3, Y direction ) directed upward from the first face ( Yang, FIG. 3, bottom surface of 348 ) to the second face ( Yang, FIG. 3, top surface of 348 );
a source structure including:
a plate ( Yang, [0053], Semiconductor layer 348 can also include isolation regions and doped regions (e.g., functioning as an array common source for 3D NAND memory strings 338, not shown); [0054], Semiconductor layer 348 may include polysilicon as the source plate of the “floating gate” type of 3D NAND memory strings ) disposed on the second face of the semiconductor layer, and
a plug ( Yang, FIG. 3, 344, 354; [0052], Plug 344 can function as the channel controlled by a source select gate of 3D NAND memory string 338; [0056], contacts 354 extending through semiconductor layer 348 ) extending from the plate ( Yang, [0053], [0054], Semiconductor layer 348 … doped regions … array common source … polysilicon as the source plate of the “floating gate” ) through the semiconductor layer ( Yang, FIG. 3, 348; [0052] );
a plurality of gate electrodes ( Yang, FIG. 3, 334; [0052], In some embodiments, 3D NAND memory strings 338 further include a plurality of control gates (each being part of a word line). Each conductor layer 334 in memory stack 333 can act as a control gate for each memory cell of 3D NAND memory string 338 ) disposed on the first face ( Yang, FIG. 3, bottom surface of 348 ) of the semiconductor layer ( Yang, FIG. 3, 348; [0052] ) and sequentially stacked on one another; and
a channel structure ( Yang, FIG. 3, 342; [0051], semiconductor channel 342 ) that extends through the plurality of gate electrodes ( Yang, FIG. 3, 334; [0052] ) and that is disposed on the plug ( Yang, FIG. 3, 344; [0052] ), wherein the channel structure ( Yang, FIG. 3, 342; [0051] ) is electrically connected to the source structure ( Yang, FIG. 3, 344; [0052]; [0053], [0054], Semiconductor layer 348 … doped regions … array common source … polysilicon as the source plate of the “floating gate” ).
Yang fails to disclose:
wherein a lower surface of the plug is coplanar with the first face of the semiconductor layer.
However, Son teaches:
wherein a lower surface of the plug ( Son, FIG. 2A, 540; [0020], contact plugs 540 ) is coplanar ( Son, [0108], an upper portion of the capping layer may be planarized until the upper surface of the fifth insulating interlayer 340 may be exposed, and thus the capping pattern 430 may be formed ) with the first face of the semiconductor layer ( Son, FGI. 2a, 430 and 340; [0048], capping pattern 430; [0045], insulating layer 340 ).
Yang and Son are both considered to be analogous to the claimed invention because they are forming semiconductor memory devices. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Yang ( [0054], Semiconductor layer 348 may include polysilicon as the source plate ), to incorporate the teachings of Son ( [0108], an upper portion of the capping layer may be planarized ), to implement the precise and direct contact between plug ( Son, contact plugs 540 ) and channel ( Son, channel 410 connected with capping pattern 430 ). Doing so would improve the yield rate of contact, and reduce the contact resistance between plug and channel.
Regarding Claim 2 (Original), Yang and Son teach the semiconductor memory device as claimed in claim 1, on which this claim is dependent,
Yang does not explicitly teach:
wherein a width of the plug increases as the plug extends in a direction from the second face of the semiconductor layer toward the first face of the semiconductor layer.
However, Yang teaches: FIG. 3, 346; [0052], In some embodiments, each 3D NAND memory string 338 includes two plugs 344 and 346 ( ps. FIG. 3, the width of plug 346 increases as it extends in the direction from the second face of the semiconductor layer toward the first face of the semiconductor layer ) at a respective end in the vertical direction. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to make the shape of plug 344 by duplicating the shape of plug 346, because they are both plugs and connected with channel, and then create that wherein a width of the plug increases as the plug extends in a direction from the second face of the semiconductor layer toward the first face of the semiconductor layer, since this is within the skill level of one in the art.
Regarding Claim 3 (Original), Yang and Son teach the semiconductor memory device as claimed in claim 1, on which this claim is dependent, Yang further teaches:
wherein the plug ( Yang, FIG. 3, 344; [0052] ) includes a first plug and a second plug spaced apart from each other along a direction ( Yang, FIG. 3, multiple plugs 344 along X direction ) parallel to the first face of the semiconductor layer, and
wherein the channel structure ( Yang, FIG. 3, 342; [0051] ) includes a first channel structure disposed on the first plug, and a second channel structure disposed on the second plug ( Yang, FIG. 3, multiple channel structures 342 along X direction ).
Regarding Claim 4 (Original), Yang and Son teach the semiconductor memory device as claimed in claim 1, on which this claim is dependent, Yang further teaches:
wherein the channel structure ( Yang, FIG. 3, 342; [0051] ) includes a first channel structure and a second channel structure disposed on the plug ( Yang, FIG. 3, 344; [0052] ), and spaced apart from each other along a direction parallel to the first face of the semiconductor layer( Yang, FIG. 3, multiple plugs 344 and multiple channel structures 342 along X direction ).
Regarding Claim 5 (Original), Yang and Son teach the semiconductor memory device as claimed in claim 1, on which this claim is dependent, Yang further teaches:
wherein a top face of the channel structure in the first direction is disposed in the plug ( Yang, FIG. 3, “top of 342” in contact with 344; [0052], Plug 344 can be at the upper end of 3D NAND memory string 338 and in contact with semiconductor channel 342 ).
Regarding Claim 9 (Original), Yang and Son teach the semiconductor memory device as claimed in claim 1, on which this claim is dependent, Yang further teaches:
wherein the device further comprises a cell contact ( Yang, [0052], In some embodiments, 3D NAND memory strings 338 further include a plurality of control gates (each being part of a word line). Each conductor layer 334 in memory stack 333 can act as a control gate for each memory cell of 3D NAND memory string 338 ) that extends through the plurality of gate electrodes ( Yang, FIG. 3, 334; [0052] ) and that is electrically connected to at least one of the plurality of gate electrodes ( Yang, FIG. 3, 334; [0052] ), and
wherein a top face of the cell contact ( Yang, [0052], Each conductor layer 334 in memory stack 333 can act as a control gate for each memory cell of 3D NAND memory string 338 ) in the first direction is disposed ( Yang, FIG. 3, 344; [0052], Plug 344 can function as the channel controlled by a source select gate of 3D NAND memory string 338 ) in the semiconductor layer ( Yang, FIG. 3, 348; [0052] ).
Regarding Claim 10 (Original), Yang and Son teach the semiconductor memory device as claimed in claim 9, on which this claim is dependent, Yang further teaches:
wherein the top face of the cell contact ( Yang, [0052], Each conductor layer 334 in memory stack 333 can act as a control gate for each memory cell of 3D NAND memory string 338; FIG. 3, 344; [0052], Plug 344 can function as the channel controlled by a source select gate of 3D NAND memory string 338) in the first direction is closer to the second face ( Yang, FIG. 3, top surface of 348 ) of the semiconductor layer ( Yang, FIG. 3, 348; [0052] ) than a top face of the channel structure ( Yang, FIG. 3, 342; [0051] ) in the first direction.
Regarding Claim 11 (Original), Yang and Son teach the semiconductor memory device as claimed in claim 9, on which this claim is dependent, Yang further teaches:
wherein the cell contact ( Yang, [0052], Each conductor layer 334 in memory stack 333 can act as a control gate for each memory cell of 3D NAND memory string 338 ) is spaced apart from the source structure ( Yang, FIG. 3, 344, 354; [0052] ) along a direction parallel to the first face ( Yang, FIG. 3, bottom surface of 348 ) of the semiconductor layer ( Yang, FIG. 3, 348; [0052] ).
Regarding Claim 12 (Original), Yang and Son teach the semiconductor memory device as claimed in claim 1, on which this claim is dependent, Yang further teaches:
wherein the device further comprises a source contact ( Yang, [0052], Plug 344 can function as the channel controlled by a source select gate of 3D NAND memory string 338; [0053], an array common source for 3D NAND memory strings 338, not shown ) that extends through the plurality of gate electrodes ( Yang, FIG. 3, 334; [0052] ) and that is electrically connected to the source structure ( [0053], Semiconductor layer 348 can also include isolation regions and doped regions (e.g., functioning as an array common source for 3D NAND memory strings 338, not shown) ).
Regarding Claim 13 (Original), Yang and Son teach the semiconductor memory device as claimed in claim 12, on which this claim is dependent, Yang further teaches:
wherein a top face of the source contact ( Yang, [0052], Plug 344 can function as the channel controlled by a source select gate of 3D NAND memory string 338; [0053], an array common source for 3D NAND memory strings 338, not shown ) in the first direction is disposed in the plug ( Yang, FIG. 3, 344; [0052] ).
Regarding Claim 14 (Original), Yang and Son teach the semiconductor memory device as claimed in claim 1, on which this claim is dependent, Yang further teaches:
wherein a gate electrode ( Yang, FIG. 3, 334; [0052] ) closest ( Yang, FIG. 3, the top one of 334 ) to the first face ( Yang, FIG. 3, bottom surface of 348 ) of the semiconductor layer ( Yang, FIG. 3, 348; [0052] ) among the plurality of gate electrodes ( Yang, FIG. 3, 334; [0052] ) includes a third face ( Yang, FIG. 3, the top surface of the top one of 334 ) facing the first face ( Yang, FIG. 3, bottom surface of 348 ), and
wherein the third face ( Yang, FIG. 3, the top surface of the top one of 334 ) of the gate electrode ( Yang, FIG. 3, 334; [0052] ) is closer to the first face ( Yang, FIG. 3, bottom surface of 348 ) of the semiconductor layer ( Yang, FIG. 3, 348; [0052] ) than a bottommost face of the plug ( Yang, FIG. 3, 344; [0052 ) in the first direction.
Regarding Claim 15 (Original), Yang and Son teach the semiconductor memory device as claimed in claim 1, on which this claim is dependent, Yang further teaches:
wherein the channel structure (Yang, FIG. 3, 342; [0051]) includes a portion (Yang, FIG. 3, under 344, the portion between 342), wherein a width of the portion decreases (Yang, FIG. 3, the width of portion decreases from bottom to top) as the portion extends in a direction from the first face (Yang, FIG. 3, bottom surface of 348) to the second face (Yang, FIG. 3, top surface of 348) of the semiconductor layer (Yang, FIG. 3, 348; [0052]).
Claims 6 – 8 are rejected under 35 U.S.C. 103 as being unpatentable over Yang, in view of Son, further in view of Xu ( Pub. No. US 20200243557 A1 ), hereinafter Xu.
Regarding Claim 6 (Original), Yang and Son teach the semiconductor memory device as claimed in claim 1, on which this claim is dependent,
Yang and Son fail to teach:
wherein the device further comprises a word-line cutting structure that extends through the plurality of gate electrodes and cuts the plurality of gate electrodes, and
wherein a top face of the word-line cutting structure in the first direction is disposed in the semiconductor layer.
However, Xu teaches:
wherein the device further comprises a word-line cutting structure ( Xu, FIG. 8A, 221, 222; [0083], gate line slits 221 and 222 ) that extends through the plurality of gate electrodes and cuts the plurality of gate electrodes ( Xu, [0082], The formed gate line slits electrically insulate and separate adjacent fingers and subsequently-formed word lines of different tiers at locations filled with the insulating material ), and
wherein a top face of the word-line cutting structure in the first direction is disposed in the semiconductor layer ( Xu, [0085], The insulating material can then be deposited at the bottom and over the sidewall of the vertical trench … Thus, the insulating material can provide electrical insulation between the source contact via and the rest of stack 240′ ).
Yang and Son and Xu are all considered to be analogous to the claimed invention because they are forming semiconductor memory devices. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Yang ( Semiconductor layer 348 can also include isolation regions and doped regions ) and Son ( an upper portion of the capping layer may be planarized ) to incorporate the teachings of Xu ( gate line slits electrically insulate and separate adjacent fingers and subsequently-formed word lines of different tiers at locations filled with the insulating material ) by incorporating Xu’s gate line slit into the device taught by Yang and Son, and implement that a word-line cutting structure that extends through the plurality of gate electrodes and cuts the plurality of gate electrodes. Doing so the semiconductor memory can be divided into a plurality of memory cell blocks via the word-line cutting structures, and therefore reduce power consumption and improve reliability.
Regarding Claim 7 (Original), Yang, Son and Xu teach the semiconductor memory device as claimed in claim 6, on which this claim is dependent, Yang further teaches:
the second face ( Yang, FIG. 3, top surface of 348 ) of the semiconductor layer ( Yang, FIG. 3, 348; [0052] ), a top face of the channel structure ( Yang, FIG. 3, 342; [0051] ) in the first direction.
Yang and Son fail to teach:
Wherein the top face of the word-line cutting structure in the first direction is closer to the second face of the semiconductor layer than a top face of the channel structure in the first direction.
However, Xu teaches:
The word-line cutting structure ( Xu, FIG. 8A, 221, 222; [0083], gate line slits 221 and 222; [0082], The formed gate line slits electrically insulate and separate adjacent fingers and subsequently-formed word lines of different tiers at locations filled with the insulating material; [0085], The insulating material can then be deposited at the bottom and over the sidewall of the vertical trench … Thus, the insulating material can provide electrical insulation between the source contact via and the rest of stack 240′ ).
Yang, Son and Xu are all considered to be analogous to the claimed invention because they are forming semiconductor memory devices. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Yang ( the top surface of Semiconductor layer 348 is higher than the top surface of channel structure 342, more than the height of plus 344 ) and Son ( an upper portion of the capping layer may be planarized ) to incorporate the teachings of Xu ( gate line slits electrically insulate and separate adjacent fingers and subsequently-formed word lines of different tiers at locations filled with the insulating material ) by incorporating Xu’s gate line into the device taught by Yang and Son, and the top surface of Xu’s gate line I is above the top surface of Yang’s plug 344, in order to completely isolate word lines, and therefore to achieve that wherein the top face of the word-line cutting structure in the first direction is closer to the second face of the semiconductor layer than a top face of the channel structure in the first direction. Doing so the semiconductor memory can be divided into a plurality of memory cell blocks via the word-line cutting structures, and therefore reduce power consumption and improve reliability.
Regarding Claim 8 (Original), Yang, Son and Xu teach the semiconductor memory device as claimed in claim 6, on which this claim is dependent, Yang further teaches:
the source structure (Yang, FIG. 3, 344, 354; [0052], Plug 344) along a direction parallel to the first face ( Yang, FIG. 3, bottom surface of 348 ) of the semiconductor layer.
Yang and Son fail to teach:
Wherein the word-line cutting structure is spaced apart from the source structure along a direction parallel to the first face of the semiconductor layer.
However, Xu teaches:
The word-line cutting structure ( Xu, FIG. 8A, 221, 222; [0083], gate line slits 221 and 222; [0082], The formed gate line slits electrically insulate and separate adjacent fingers and subsequently-formed word lines of different tiers at locations filled with the insulating material; [0085], The insulating material can then be deposited at the bottom and over the sidewall of the vertical trench … Thus, the insulating material can provide electrical insulation between the source contact via and the rest of stack 240′ ).
Yang, Son and Xu are all considered to be analogous to the claimed invention because they are forming semiconductor memory devices. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Yang ( the source structure, plus 344 ) and Son ( an upper portion of the capping layer may be planarized ) to incorporate the teachings of Xu ( gate line slits electrically insulate and separate adjacent fingers and subsequently-formed word lines of different tiers at locations filled with the insulating material ) by incorporating Xu’s gate line into the device taught by Yang and Son, and therefore to achieve that wherein the word-line cutting structure is spaced apart from the source structure along a direction parallel to the first face of the semiconductor layer. Doing so the semiconductor memory can be divided into a plurality of memory cell blocks via the word-line cutting structures, and therefore reduce power consumption and improve reliability.
Response to Arguments
Applicant's arguments filed 2/26/2026 have been fully considered but they are not persuasive.
Applicant’s remarks regarding Claim 1: on page 1, line 6 from bottom, cited “ Applicant has amended independent claim 1 to recite "wherein a lower surface of the plug is coplanar with the first face of the semiconductor layer." Support for this amendment is found in the specification at least at [0054]. As agreed during the interview, this limitation is not disclosed by either Yang or Xu whether alone or in combination. … Yang's plugs (allegedly corresponding to the claimed plug) lack a lower surface "coplanar with the first face of the semiconductor layer" as required in claim 1. Xu fails to cure the deficiencies of Yang. ”.
Examiner’s response: please refer to claim 1 in Claim Rejections - 35 USC § 103 of this office action, cited “ However, Son teaches:
wherein a lower surface of the plug ( Son, FIG. 2A, 540; [0020], contact plugs 540 ) is coplanar ( Son, [0108], an upper portion of the capping layer may be planarized until the upper surface of the fifth insulating interlayer 340 may be exposed, and thus the capping pattern 430 may be formed ) with the first face of the semiconductor layer ( Son, FGI. 2a, 430 and 340; [0048], capping pattern 430; [0045], insulating layer 340 ).
Yang and Son are both considered to be analogous to the claimed invention because they are forming semiconductor memory devices. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Yang ( [0054], Semiconductor layer 348 may include polysilicon as the source plate ), to incorporate the teachings of Son ( [0108], an upper portion of the capping layer may be planarized ), to implement the precise and direct contact between plug ( Son, contact plugs 540 ) and channel ( Son, channel 410 connected with capping pattern 430 ). Doing so would improve the yield rate of contact, and reduce the contact resistance between plug and channel.”.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Da-Wei Lee whose telephone number is 703-756-1792. The examiner can normally be reached M -̶ F 8:00 am -̶ 6:00 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DA-WEI LEE/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817