Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Election was made without traverse in the reply filed on 12/16/2025. Applicant has elected Group II, corresponding to claims 1-7. Invention Group I, corresponding to claims 8-14, is withdrawn from further consideration.
Specification
The specification submitted 3/8/2023 has been accepted by the examiner.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 3/8/2023 has been considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Claim 7: The semiconductor memory device according to claim 6, further comprising
a third semiconductor part provided on the cap layer.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Zhao (US # 20210159169).
Regarding Claim 1, Zhao (US # 20210159169) teaches a semiconductor memory device (see Figs. 1 and 15 and corresponding text) comprising:
a peripheral circuit ([0034] teaches about peripheral devices such as device 700) provided on a surface (top) of a semiconductor substrate (9, 10); and
a memory cell array (100) provided above the peripheral circuit, wherein
the memory cell array includes:
a stack (32, 46W, 46S, 46D) having conductive layers (46W, 46S, 46D) and insulating layers (32), each conductive layer and each insulating layer being alternately stacked and extending in a first direction (horizontal across the page),
the conductive layers including
a first select gate line (46S) connected to a gate of a first select transistor (shown in Fig. 16, and see [0102]),
a word line (46W) provided above the first select gate line and connected to a gate of a memory transistor (see [0102]), and
a second select gate line (46D) provided above the word line and connected to a gate of a second select transistor (see [0102]);
a core insulating layer (see Fig. 15, feature 62) extending in a second direction (into the page) intersecting the first direction, the core insulating layer having a top surface lower than a
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top surface of the second select gate line with respect to the surface of the semiconductor substrate (shown in Fig. 15);
a semiconductor layer (60) extending in the second direction, the semiconductor layer having a first semiconductor part (602, 601) and a second semiconductor part (603), the first semiconductor part having channel formation regions of the memory transistor (portions of 602,601 correspond to each vertically stacked memory cell) and the first and second select transistors, and the second semiconductor part being provided on the top surface of the core insulating layer (shown above 62); and
a memory layer (50) provided between the semiconductor layer and the stack in the first direction (shown), and
the first semiconductor part has an impurity semiconductor region containing an impurity element ([0073] explains dopant concentrations and conductivity type) and overlapping with the second select gate line (and horizontal overlap with 46D is shown).
Regarding Claim 2, Zhao teaches the semiconductor memory device according to claim 1, wherein the impurity semiconductor region contains arsenic (second conductivity type, arsenic and phosphorous is taught in [0124]).
Regarding Claim 3, Zhao teaches the semiconductor memory device according to claim 1, wherein the second select transistor is configured to cause Gate Induced Drain Leakage in response to a reverse bias voltage to be applied between the gate and a drain of the second select transistor ([0153] explains the use of GIDL for erase operations; overlap between the drain region and the drain select gate electrode enhances the electrical field that induces the gate-induced leakage current.).
Regarding Claim 4, Zhao teaches the semiconductor memory device according to claim 1, further comprising a cap layer (63) provided on the second semiconductor part (shown most clearly in Fig. 5I).
Regarding Claim 5, Zhao teaches the semiconductor memory device according to claim 4, wherein the cap layer contains silicon doped with phosphorus (see [0080]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Zhao (US # 20210159169) in view of Zhang (US # 20210375912).
Regarding Claim 6, although Zhao discloses much of the claimed invention, it does not explicitly teach the semiconductor memory device according to claim 4, wherein the cap layer contains silicon oxide.
Nonetheless the prior art at the time the application was filed renders such non-explicit feature differences obvious, as explained below.
For example, Zhang is in the same or analogous field, and it teaches a semiconductor memory device wherein a cap layer contains silicon oxide ([0044]).
A person having ordinary skill in the art would have recognized that modifying the capping material of Zhao with the capping material suggested by Zhang would be obvious. Specifically, the modification suggested by Zhang would be to employ a semiconductor memory device according to claim 4, wherein the cap layer contains silicon oxide. It would have been obvious to one of ordinary skill in the art at the time the claimed invention was made to use silicon oxide for a capping layer since it has been held by the courts that selection of a prior art material on the basis of its suitability for its intended purpose is within the level of ordinary skill. In re Leshing, 125 USPQ 416 (CCPA 1960) and Sinclair & Carroll Co. v. Interchemical Corp., 65 USPQ 297 (1945). This material is known to prevent impurity diffusion and protect underlying structures.
Allowable Subject Matter
Claim 7 would be allowable if rewritten to overcome the drawing objections set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 9711524
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/CHRISTOPHER A JOHNSON/ Primary Examiner, Art Unit 2899