Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Election was made without traverse in the reply filed on 12/16/2025. Applicant has elected Group II, corresponding to claims 1-8 and 15. Invention Group I, corresponding to claims 9-14, is withdrawn from further consideration.
Specification
The specification submitted 3/08/2023 has been accepted by the examiner.
Drawings
The drawings submitted on 3/08/2023 have been accepted by the examiner.
Information Disclosure Statements
The information disclosure statements (IDS) submitted recently have been considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8 are rejected under 35 U.S.C. 103 as being unpatentable over Lim (US # 20080157383) in view of Hsu (US # 5796151) and further in view of Park (US # 20010035557) and Melde (US # 9842845).
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Regarding Claim 1, Lim (US 20080157383) teaches a semiconductor device (see Fig. 10C and corresponding text), comprising:
a semiconductor substrate (800) containing a first-type impurity ([0225] an ion-implantation process is performed to form an isolation layer, a well and a channel);
a first insulating layer (801) provided on a region of the semiconductor substrate;
a first gate electrode having
a first semiconductor layer (21) provided on the first insulating layer and containing an impurity ([0227]),
a first conductive layer (22A) provided on the first semiconductor layer and containing titanium ([0228]),
a second conductive layer (22B) provided on the first conductive layer and containing nitrogen and either titanium or tungsten ([0228]), and
a third conductive layer (22C) provided on the second conductive layer and containing tungsten ([0228]).
Although Lim discloses much of the claimed invention, it does not explicitly teach the semiconductor substrate having a first region and a second region, each region containing a first-type impurity; the first insulating layer provided between the first region and the second region in the semiconductor substrate; a second insulating layer provided on the third conductive layer and containing oxygen and silicon; a third insulating layer provided on the second insulating layer and containing nitrogen and silicon; a first contact provided on the first region; a second contact provided on the second region; and a third contact provided on the third conductive layer of the first gate electrode, the third contact penetrating through the second insulating layer and the third insulating layer.
Nonetheless the prior art at the time the application was filed renders such non-explicit feature differences obvious, as explained below.
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For example, Hsu (US # 5796151) is in the same or analogous field, and it teaches a second insulating layer (16) provided on a third conductive layer (15) and containing oxygen and silicon (col. 2, line 21); a third insulating layer (17) provided on the second insulating layer and containing nitrogen and silicon (col. 2, line 22).
A person having ordinary skill in the art would have recognized that modifying the device of Lim with the protective layers suggested by Hsu would be obvious. Specifically, the modification suggested by Hsu would be to employ a protective layer comprising a second insulating layer provided on the third conductive layer and containing oxygen and silicon; and a third insulating layer provided on the second insulating layer and containing nitrogen and silicon. The rationale for this obvious modification is that the protective layers provides protection for the lower layers from impurities during subsequent processes.
Although Lim in view of Hsu discloses much of the claimed invention, it does not explicitly teach the semiconductor substrate having a first region and a second region, each region containing a first-type impurity; the first insulating layer provided between the first region and the second region in the semiconductor substrate; a first contact provided on the first region; a second contact provided on the second region; and a third contact provided on the third conductive layer of the first gate electrode, the third contact penetrating through the second insulating layer and the third insulating layer.
Nonetheless the prior art at the time the application was filed renders such non-explicit feature differences obvious, as explained below.
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For example, Park (US # 20010035557) is in the same or analogous field, and it teaches a semiconductor substrate (100; see Fig. 5 and corresponding text) having a first region (left of gate 60, regions 64, 70) and a second region (right of gate 60, regions 64, 70), each region containing a first-type impurity (n-type); a first insulating layer (58) provided between the first region and the second region in the semiconductor substrate (shown); a first contact (82) provided on the first region; a second contact (82) provided on the second region.
A person having ordinary skill in the art would have recognized that modifying the substrate and interconnections of Lim in view of Hsu with the impurity regions and via contacts suggested by Park would be obvious. Specifically, the modification suggested by Park would be to employ a semiconductor substrate having a first region and a second region, each region containing a first-type impurity; the first insulating layer provided between the first region and the second region in the semiconductor substrate; a first contact provided on the first region; and a second contact provided on the second region. The rationale for this obvious modification is that source/drain features and via contacts provide are very well-known for setting a voltage across the channel. This would have been apparent to a person having ordinary skill in the art in reading both references because the existence and benefits of NMOS S/D features are well known in the art (see MPEP 2144.01).
Although Lim in view of Hsu and Park discloses much of the claimed invention, it does not explicitly teach the device comprising a third contact provided on the third conductive layer of the first gate electrode, the third contact penetrating through the second insulating layer and the third insulating layer.
Nonetheless the prior art at the time the application was filed renders such non-explicit feature differences obvious, as explained below.
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For example, Melde (US # 9842845) is in the same or analogous field, and it teaches a device (110; see Fig. 2 and corresponding text) comprising a third contact (central feature of set of features 137c) provided on a conductive layer (polysilicon, amorphous silicon, an electrode metal and the like, and also including work-function adjusting layers) of a first gate electrode (gate electrode 116), the third contact penetrating through an overlying protective layer (ILD).
A person having ordinary skill in the art would have recognized that modifying the interconnections of Lim in view of Hsu and Park with the gate plug suggested by Melde would be obvious. Specifically, the modification suggested by Melde would be to employ a device comprising a third contact provided on the third conductive layer of the first gate electrode, the third contact penetrating through the second insulating layer and the third insulating layer. The rationale for this obvious modification is that a gate plug provides interconnection to the gate so that a bias can switch the channel on/off. This would have been apparent to a person having ordinary skill in the art in reading both references because the existence and benefits of gate plugs are well known in the art (see MPEP 2144.01).
Regarding Claim 2, Hsu, as applied to claim 1, does not teach the device according to claim 1, wherein the second insulating layer is thinner than the third insulating layer. Although does not teach this limitation explicitly, the examiner finds this obvious as it is a mere change of relative size. See MPEP 2144.04 also citing to In Gardnerv.TEC Syst., Inc., (725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)), where the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. The mere carrying forward of a prior-art conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions (In re Williams, 36 F.2d 436, 438 (CCPA 1929)). When there is a design need or market pressure to solve a problem and there are a finite number of identified, predictable solutions, a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense. See KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007) & MPEP 2144.05.
Regarding Claim 3, Hsu, as applied to claim 1, teaches the semiconductor device according to claim 1, wherein the second insulating layer (16) is configured to prevent oxidation of the third conductive layer (see col. 2, first paragraph).
Regarding Claim 4, Lim teaches the semiconductor device according to claim 1, wherein the first semiconductor layer contains polysilicon doped with the first-type impurity ([0050] teaches N-type impurity such as phosphorous).
Regarding Claim 5, this claim is essentially a repeat of claim 1, except for a PMOS structure instead of NMOS, and Lim in view of Hsu and further in view of Park and Melde teach the same device except for a PMOS (the same teachings include either p-type or n-type structures).
Regarding Claim 6, this claim is essentially a repeat of claim 2. It is rejected with essentially the same reasoning.
Regarding Claim 7, this claim is essentially a repeat of claim 3. It is rejected with essentially the same reasoning.
Regarding Claim 8, this claim is essentially a repeat of claim 4. It is rejected with essentially the same reasoning.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Lim (US # 20080157383) in view of Hsu (US # 5796151) and further in view of Park (US # 20010035557), Melde (US # 9842845), and Yang (US # 20210225870).
Regarding Claim 15, Lim in view of Hsu, Park, and Melde render obvious the device according to claim 1.
Although Lim in view of Hsu, Park, and Melde discloses much of the claimed invention, it does not explicitly teach a semiconductor memory device, comprising: a memory cell array; and a peripheral circuit having the semiconductor device according to claim 1.
Nonetheless the prior art at the time the application was filed renders such non-explicit feature differences obvious, as explained below.
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For example, Yang is in the same or analogous field, and it teaches a semiconductor memory device, comprising: a memory cell array (CS); and a peripheral circuit (PS).
A person having ordinary skill in the art would have recognized that modifying the device of Lim in view of Hsu, Park, and Melde with the memory & peripheral circuit configuration suggested by Yang would be obvious. Specifically, the modification suggested by Yang would be to employ a semiconductor memory device, comprising: a memory cell array; and a peripheral circuit having the semiconductor device according to claim 1. The rationale for this obvious modification is that a configuration of memory cells with peripheral circuit provides a known way of controlling the memory cells for reading/writing/erasing.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A JOHNSON whose telephone number is (571)272-9475. The examiner can normally be reached normally working Monday to Friday between 9 am and 6 pm Eastern Time.
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/CHRISTOPHER A JOHNSON/ Primary Examiner, Art Unit 2899