DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
The amended title is sufficiently specific to overcome the objection.
The deleted portion of paragraph 165 of the specification obviates the objection.
New FIG. 16 overcomes the objection to the drawings. It appears that the elements disclosed are sufficiently generically shown to not contain new matter.
The amendments to claims 18 and 20 overcome the 112 rejections.
The applicant argues on pages 11-14 of the response that the parent application provides enabling support for the present invention. The parent application does not describe or illustrate how one would implement the invention in a device. There are statements about the invention, but not an explanation of how to practice the invention. For example, the applicant quotes the parent application as stating that “[a]s shown in Fig. 1, an orthographic projection of the active layer 34 onto the base substrate may completely fall within an orthographic projection of the light-shielding pattern 33 onto the base substrate”. However, all that is shown is two rectangles. Is this one active layer of a single transistor? If so, what is the light-shielding pattern 33? The light shielding pattern appears to be a layer covering a large portion of the display with holes in it. It is now clear that there is a light shielding portion for each transistor that is between the holes. This cannot be determined from the original figures. As the Federal Circuit set forth, “[a]lthough the knowledge of one skilled in the art is indeed relevant, the novel aspect of an invention must be enabled in the patent.” Automotive Tech. V. BMW OF N. Am., 501 F.3d 1274, 1283 (Fed. Cir. 2007), emphasis added. Expecting the invention to be implemented without clear guidance is not fulfilling the qui pro quo of patent law.
See the new rejections below.
Priority Date
This application is a continuation-in-part of application 16/346,435. As explained by the examiner in that application, the examiner does not believe that application 16/346,435 is enabling for the invention, as it has no useful figures to implement the invention and the written description addresses the invention in general terms. Therefore the priority date for this application is deemed to be the current filing date, March 8, 2023.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-5 and 7-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “adjacent first pixel circuits”, as do claims 14 and 20. Previously recited is “a first pixel circuit and a first light emitting element, the first pixel circuit is configured to drive the first light-emitting element to emit light”. Having adjacent first pixel circuits require multiple first pixel circuits, which are not recited. For present purposes the examiner will assume that there are multiple first pixel circuits for multiple pixels.
The remaining claims are rejected based on their dependencies.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 14, 15, and 20 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Ko, US 2019/0095674 A1.
Claim 1: Ko discloses a display substrate, wherein the display substrate comprises an effective display region (DA), the effective display region comprises a first region (SA) and other display regions located on at least one side of the first region (FIG. 1), a transmittance of the first region is greater than transmittances of the other display regions, and the display substrate comprises:
a base substrate (111);
a plurality of first pixels (PXL) in the first region, located at a side of the base substrate, wherein at least one of the plurality of first pixels comprises a first pixel circuit (PXLC) and a first light emitting element (EL), the first pixel circuit is configured to drive the first light-emitting element to emit light, and the first pixel circuit comprises a thin film transistor (M);
and a light-shielding layer (300, [0109]), located between the base substrate and the first pixel circuit, the light-shielding layer comprises a shielding portion located in the first region (FIG. 5A);
a plurality of imaging holes (LTH) arranged in an array, the plurality of imaging holes are arranged in the shielding portion of the light-shielding layer, and the plurality of imaging holes are configured to enable the light to transmitted therethrough ([0109], FIG. 5A).
Claim 1 also recites that an orthographic projection of the first pixel circuit onto the base substrate is located within an orthographic projection of the shielding portion onto the base substrate; and that an imaging hole is configured to correspond to a gap between adjacent first pixel circuits. Ko discloses at [0110] that “the light-guiding layer 300 may include a plurality of light-transmission holes LTH corresponding to respective light-receiving units of the photosensors PHS, and each light-transmission hole LTH may overlap the light-receiving unit of the photosensor PHS corresponding thereto.” As shown in FIG. 5B, each of the openings LTH corresponds to (is slightly smaller than) the photosensor PHS. As seen in FIG. 3G, the photosensors PHS can be entirely non-overlapping with the pixels PXL, which include the pixel circuits PXLC (see e.g. FIG. 4C). As the hole is slightly smaller than the photosensor, the hole will correspond to a gap between adjacent first pixel circuits, and the first pixel circuit will be within the non-hole part (the shielding portion).
PNG
media_image1.png
386
704
media_image1.png
Greyscale
Claim 2: the display substrate further comprises:
a plurality of second pixels in the other display regions, located at the side of the base substrate, wherein at least one of the plurality of second pixels comprises a second pixel circuit (PXLC outside SA) and a second light emitting element (EL outside SA), the second pixel circuit is configured to drive the second light emitting element to emit light, and the second pixel circuit comprises a thin film transistor (M);
and wherein the light-shielding layer further comprises a first light-shielding pattern in the other display regions, and an orthographic projection of the second pixel circuit onto the base substrate is located within an orthographic projection of the first light-shielding pattern onto the base substrate. As seen in FIGS. 5A and 5B, the light shielding layer extends through the entire substrate. As explained with respect to claim 1, the first pixel circuit will be within the non-hole part (the shielding portion).
Claim 14: Ko discloses a display device (abstract), comprising a display substrate, wherein the display substrate comprises an effective display region (DA), the effective display region comprises a first region (SA) and other display regions located on at least one side of the first region (FIG. 1), a transmittance of the first region is greater than transmittances of the other display regions, and the display substrate comprises:
a base substrate (301 and/or 400);
a plurality of first pixels (PXL) in the first region, located at a side of the base substrate, wherein at least one of the plurality of first pixels comprises a first pixel circuit (PXLC) and a first light emitting element (EL), the first pixel circuit is configured to drive the first light-emitting element to emit light, and the first pixel circuit comprises a thin film transistor (M);
and a light-shielding layer (300, [0109]), located between the base substrate and the first pixel circuit, the light-shielding layer comprises a shielding portion located in the first region (FIG. 5A);
a plurality of imaging holes (LTH) arranged in an array, the plurality of imaging holes are arranged in the shielding portion of the light-shielding layer, and the plurality of imaging holes are configured to enable the light to transmitted therethrough ([0109], FIG. 5A);
and wherein the display device further comprises: a sensor (PHS), arranged at another side of the base substrate facing away from the plurality of first pixels (FIG. 5B).
Claim 14 also recites that an orthographic projection of the first pixel circuit onto the base substrate is located within an orthographic projection of the shielding portion onto the base substrate; and that an imaging hole is configured to correspond to a gap between adjacent first pixel circuits. Ko discloses at [0110] that “the light-guiding layer 300 may include a plurality of light-transmission holes LTH corresponding to respective light-receiving units of the photosensors PHS, and each light-transmission hole LTH may overlap the light-receiving unit of the photosensor PHS corresponding thereto.” As shown in FIG. 5B, each of the openings LTH corresponds to (is slightly smaller than) the photosensor PHS. As seen in FIG. 3G, the photosensors PHS can be entirely non-overlapping with the pixels PXL, which include the pixel circuits PXLC (see e.g. FIG. 4C). As the hole is slightly smaller than the photosensor, the hole will correspond to a gap between adjacent first pixel circuits, and the first pixel circuit will be within the non-hole part (the shielding portion).
Claim 15: the display substrate further comprises:
a plurality of second pixels in the other display regions, located at the side of the base substrate, wherein at least one of the plurality of second pixels comprises a second pixel circuit (PXLC outside SA) and a second light emitting element (EL outside SA), the second pixel circuit is configured to drive the second light emitting element to emit light, and the second pixel circuit comprises a thin film transistor (M);
and wherein the light-shielding layer further comprises a first light-shielding pattern in the other display regions, and an orthographic projection of the second pixel circuit onto the base substrate is located within an orthographic projection of the first light-shielding pattern onto the base substrate. As seen in FIGS. 5A and 5B, the light shielding layer extends through the entire substrate. As explained with respect to claim 1, the first pixel circuit will be within the non-hole part (the shielding portion).
Claim 20: Ko discloses a method for manufacturing a display substrate, the display substrate comprising an effective display region (DA), the effective display region comprising a first region (SA) and other display regions located on at least one side of the first region, a transmittance of the first region being greater than transmittances of the other display regions, wherein the method comprises:
forming a base substrate (111);
forming a light-shielding layer (300, [0109]) on the base substrate, comprising: forming a shielding portion located in the first region, and forming a plurality of imaging holes (LTH) arranged in an array, the plurality of imaging holes is configured to enable the light to transmitted therethrough (FIG. 5A);
PNG
media_image2.png
538
454
media_image2.png
Greyscale
forming a thin film transistor array on the light-shielding layer, the thin film transistor array comprising a plurality of first pixels in the first region, at least one of the plurality of first pixels comprising a first pixel circuit and a first light emitting element, the first pixel circuit being configured to drive the first light-emitting element to emit light, the first pixel circuit comprising a thin film transistor (M);
and forming an anode (ELT1), a light-emitting layer (EML), and a cathode (ELT2) on the thin film transistor array.
Claim 20 also recites that an orthographic projection of the first pixel circuit onto the base substrate being located within an orthographic projection of the shielding portion onto the base substrate, and an imaging hole is configured to correspond to a gap between adjacent first pixel circuits. Ko discloses at [0110] that “the light-guiding layer 300 may include a plurality of light-transmission holes LTH corresponding to respective light-receiving units of the photosensors PHS, and each light-transmission hole LTH may overlap the light-receiving unit of the photosensor PHS corresponding thereto.” As shown in FIG. 5B, each of the openings LTH corresponds to (is slightly smaller than) the photosensor PHS. As seen in FIG. 3G, the photosensors PHS can be entirely non-overlapping with the pixels PXL, which include the pixel circuits PXLC (see e.g. FIG. 4C). As the hole is slightly smaller than the photosensor, the hole will correspond to a gap between adjacent first pixel circuits, and the first pixel circuit will be within the non-hole part (the shielding portion).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-5 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Ko in view of Li, CN109697396.
Claim 3 and 16: Ko does not disclose the size of pixel circuit on the base, and thus does not disclose the relative sizes in the regions. However, see Li, which discloses that “in FIG. 6a and FIG. 6b, the pixel 200 of the thin film transistor layer 220, the thin film transistor layer corresponding to the fingerprint identification region 111 of the area of the source/drain electrode and grid electrode 220 is less than the effective display corresponding to other areas in the area of thin film transistor layer 220 in the source-drain electrode and the grid electrode area, also can reduce the effect of pixel 200 area. and reducing the source-drain electrode and grid electrode of the light barrier.” ([0057].) Thus it was known in the art to have a size of the orthographic projection of the first pixel circuit in the first region onto the base substrate be smaller than a size of the orthographic projection of the second pixel circuit in the other display regions onto the base substrate. As the light shield is to protect the circuit, the size of the light shield will also be smaller in the optical area.
Claim 4: a distance between two adjacent first pixel circuits in the first region is greater than a distance between two adjacent second pixel circuits in the other display regions. See Li, FIGS. 5 and 7.
PNG
media_image3.png
412
520
media_image3.png
Greyscale
Claim 5: Li discloses that the density of the optical area is lower than the density in other areas in order to allow for higher quality fingerprint recognition. [0058]-[0059]. Thus the density of the pixels is a known result-effective variable: decreasing the density reduces the image quality, but increases the transmittance and thus the fingerprint detection quality. It would have been within ordinary skill in the art to determine the proper optimization of the pixel density (number of pixels per inch) of the first region. See 2144.05(II)B.
Claims 7, 9, 10, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Ko in view of Jin, US 2020/70020737 or Yeke Yazdandoost, US 2019/0310724.
Claim 7: Ko discloses first region SA that is a fingerprint region ([0054]). Claim 7 recites a second region with the same properties as the first region. This is obvious as a duplication of parts. That is, there could be multiple fingerprint regions (or potentially other types of optical regions). As evidence that this was known in the art, see Jin FIG. 9, [0037] (two fingerprint regions); Yeke Yazdandoost, [0037] (other optical regions).
PNG
media_image4.png
454
510
media_image4.png
Greyscale
In a case of multiple fingerprint regions, the second fingerprint area (the “second region” recited in claim 7) would be the same as the first, and would have a transmittance of the second region is greater than the transmittances of the other display regions (Li [0037]), the display substrate further comprises:
a plurality of third pixels (30) in the second region, located at the side of the base substrate, at least one of the plurality of third pixels comprises a third pixel circuit (20) and a third light emitting element (300), the third pixel circuit is configured to drive the third light emitting element to emit light, and the third pixel circuit comprises a thin film transistor (those in the art would recognize the transistors in the figures as TFTs);
and wherein the light-shielding layer further comprises a second light-shielding pattern (80) in the second region, and an orthographic projection of the third pixel circuit onto the base substrate is located within an orthographic projection of the second light-shielding pattern onto the base substrate (FIG. 7).
This would also be obvious for other optical elements, as light would need to pass to any element that interacts with light from the front of the device.
Claim 9: the shielding portion, the first shielding pattern and the second shielding pattern are located in the same layer and comprise the same material (300, Ko FIGS. 5A and 5B).
Claim 10: as the first and second regions of Jin serve the same function (fingerprint detection), and the first and second light-shielding patterns have the same function in the respective areas, it would have been obvious and expected for the first light-shielding pattern, the second light-shielding pattern, and respective active layers have substantially the same size and shape, wherein the respective active layers are active layers of thin film transistors corresponding to the first light-shielding pattern and the second light-shielding pattern, respectively.
Claim 12: Ko in view of Jin or Yeke Yazdandoost would have the second light-shielding pattern comprising at least two light-shielding portions, and in the second region, active layers of at least two thin film transistors are arranged on a light-shielding portion in the second light-shielding pattern, as they are in all regions of Ko. Yeke Yazdandoost, FIG. 2A, discloses that second region (over imaging array 214) with at pixels 208 arranged on one light-shielding portion (210). As shown by Ko and other references of record, each of the pixels has a transistor with an active layer, and thus for these pixels over the light shielding portion 210, an active layer of at least one thin film transistor adjacent to the at least two thin film transistors would be arranged on this light-shielding portion in the second light-shielding pattern.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Ko in view of Jin or Yeke Yazdandoost and further in view of Li, CN 109697396. Ko does not disclose the size of pixel circuit on the base, and thus does not disclose the relative sizes in the regions. However, see Li, which discloses that “in FIG. 6a and FIG. 6b, the pixel 200 of the thin film transistor layer 220, the thin film transistor layer corresponding to the fingerprint identification region 111 of the area of the source/drain electrode and grid electrode 220 is less than the effective display corresponding to other areas in the area of thin film transistor layer 220 in the source-drain electrode and the grid electrode area, also can reduce the effect of pixel 200 area. and reducing the source-drain electrode and grid electrode of the light barrier.” ([0057].) Thus it was known in the art to have a size of the orthographic projection of the second pixel circuit in the second region onto the base substrate be smaller than a size of the orthographic projection of the second pixel circuit in the other display regions onto the base substrate. As the light shield is to protect the circuit, the size of the light shield will also be smaller in the optical area.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Ko in view of Jin or Yeke Yazdandoost and further in view of Kim, 2011/0147757, and Zhou, US 2022/0376212. It was very common in the art to have facial recognition and distance detection elements on mobile devices. Thus in a mobile device application, it would have been obvious to have the claimed arrangement in claim 11. Yeke Yazdandoost, [0037]: “The optical imaging array can be used by the electronic device for any suitable imaging, sensing, or data aggregation purpose including … proximity sensing; biometric imaging (e.g., fingerprint imaging, iris imaging, facial recognition, and so on); and the like.” See FIG. 1B, which shows the imaging elements 114 (including proximity (distance) sensor and a facial recognition sensor), arranged opposite processor 116. Yeke Yazdandoost discloses at [0061] that “processor 116 can be any suitable single-core or multi-core processor capable to execute instructions stored in a memory (not shown) to instantiate one or more classes or objects configured to interface with an input or output of one or more of the optical imaging array 114”. Thus the processor 116 falls under the broadest reasonable interpretation of a face recognition circuit and a distance detection circuit, as it would be a circuit that would perform these functions. Thus here the second region that comprises a first sub-region and a second sub-region, and the first sub-region and the second sub-region are arranged to be opposite to a face recognition circuit and a distance detection circuit, respectively. As noted above, it would have been obvious to have had light shielding portions in the entire display, and would be particularly obvious in the optical regions such as these sub-regions, as they are in a region that allows light to pass. “[T]he light-shielding metal block 12, which reduces interference of external light on the conductive channel 153 and improves stability of a pixel driving circuit in the display panel 100, thereby improving performance of the display panel 100.” Zhou [0038].
PNG
media_image5.png
378
514
media_image5.png
Greyscale
Claim 11 also recites that a light-shielding portion of the second light-shielding pattern located in at least one of the first sub-region and the second sub-region is capable of blocking infrared light. Many known light shielding materials were opaque to infrared; see the light blocking layer 112 of Kim, which is made of molybdenum ([0065]), which is opaque to infrared.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Ko in view of Zhang, US 2018/0331205. The thin film transistor of Ko has a top-gate structure (FIG. 5B). Ko does not disclose that an orthographic projection of an active layer of the thin film transistor (abstract) onto the base substrate falls within an orthographic projection of a gate electrode of the thin film transistor onto the base substrate. However, this was known in the art. See Zhang, which discloses a thin film transistor (abstract) has a top-gate structure, and an orthographic projection of an active layer (104) of the thin film transistor onto the base substrate (100) falls within an orthographic projection of a gate electrode (112) of the thin film transistor onto the base substrate (FIG. 2I). It would have been obvious to have had an arrangement such as that of Zhang in to reduce parasitic capacitance and improve yield ([0063]).
PNG
media_image6.png
208
500
media_image6.png
Greyscale
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Ko in view of Yeke Yazdandoost. As explained above with respect to claim 7, it would have been obvious to have had a display with multiple optical regions. Ko discloses that a device in the region can be a camera ([0116]).
Yeke Yazdandoost discloses that
the second region (e.g. 606, FIG. 6A) is adjacent to a frame of the display device, and a transmittance of the second region is greater than the transmittance of the other display regions (abstract), and the sensor comprises: a camera ([0003], [0037]), wherein an orthographic projection of the camera (e.g. facial recognition element, 214, FIG. 2A) onto the base substrate is at least partially located within the first region;
and an optical element (e.g., proximity sensor, [0037]), wherein an orthographic projection of the optical element onto the base substrate is at least partially located within the second region, and the optical element comprises at least one of a face recognition circuit, a distance detection circuit, an environment light detection circuit, and a camera.
PNG
media_image7.png
417
560
media_image7.png
Greyscale
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Ko in view of Yeke Yazdandoost, and Park, CN 102449537. Yeke Yazdandoost discloses the display device is configured to display an image with a low resolution in the second region (FIG. 18). Park, [0072], discloses a display with higher and lower resolution portion, and that remaining battery capacity can be displayed on the lower resolution portion. It would have been obvious to have had such as known in the art.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Ko in view of Yun Ho Kim, US 2019/0252645. Ko discloses that the display device is a flexible display device ([0095]). Ko does not disclose all of the elements recited in claim 19. However, these were known in the art. See Yun Ho Kim, which discloses a flexible display device (“the substrate 110 may be a flexible substrate such as a flexible substrate containing polyimide” [0042]), and the display device further comprises a bottom film (500) attached onto a non-display side of the display substrate, and a buffering shielding layer (600) located on a side of the bottom film away from the display substrate, an opening (OP) is provided in the bottom film and the buffering shielding layer at a location corresponding to the optical element arrangement region, and the sensor is arranged on the base substrate through the opening (FIG. 2). It would have been obvious to have had such an arrangement in order to include a buffer layer 600 which is capable of absorbing shock (Yun Ho Kim [0081]), and thus to protect the device.
PNG
media_image8.png
298
516
media_image8.png
Greyscale
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Zhang, CN 106709455 A, which discloses pixel circuit 115 aligned with light blocking layer 121.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER BRADFORD whose telephone number is (571)270-1596. The examiner can normally be reached 10:30-6:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469.295.9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PETER BRADFORD/Primary Examiner, Art Unit 2897
Prosecution Insights