Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Attorney Docket Number: P56232US1
Filling Date: 03/08/23
Priority Date: 05/03/22
Inventor: Hong et al
Examiner: Bilkis Jahan
DETAILED ACTION
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-7, 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Pinos et al ((US 2023/0069410 A1) in view of Tsai et al (US 2010/0072487 A1).
Regarding claim 1, Pinos discloses an electronic device (Figs. 2-3) comprising: an array of light-emitting diodes 208 (Paras. 103, 92, Fig. 3B), wherein the array of light-emitting diodes 208 comprises a first semiconductor layer of a first type 102 (Para. 72), wherein the first semiconductor layer forms a common cathode for the array of light-emitting diodes (Paras. 103, 98), and wherein each light-emitting diode 208 (each pixel has one LED) of the array of light- emitting diodes comprises: a second semiconductor layer of a second type (Para. 78, layer between 110 and 112)).
Pinos does not explicitly discloses a conductive layer that is formed on the second semiconductor layer; and a plurality of conductive vias that all directly contact the conductive layer.
However, Tsai discloses a conductive layer 180 (Fig. 2G, Para. 32, portion on the 162) that is formed on the second semiconductor layer 130 (Para. 30); and a plurality of conductive vias 180 (portion between 162) that all directly contact the conductive layer 180. Tsai teaches the above modification is used to improve light emitting efficiency of the device (abstract). It would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to combine Pinos structure with Tsai conductive layer as suggested above to improve light emitting efficiency of the device (abstract).
Regarding claim 3, Tsai further discloses the electronic device defined in claim 1, wherein the second semiconductor layer 130 of a second type is a p-type semiconductor layer and wherein the first semiconductor layer of a first type is an n-type semiconductor layer 110 (Para. 27).
Regarding claim 4, Pinos further discloses the electronic device defined in claim 1, further comprising: an additional conductive layer 116 (Fig. 2A, Para. 98) that directly contacts the first semiconductor layer 102 (Para. 72), wherein the additional conductive layer 116 and the first semiconductor layer 102 form the common cathode for the array of light-emitting diodes (Para. 98).
Regarding claim 5, Pinos further discloses the electronic device defined in claim 4, wherein the additional conductive layer 116 is formed in a grid that defines a plurality of openings (Fig. 2A) and wherein each light- emitting diode 210 in the array of light-emitting diodes is formed in a respective opening (Fig. 2A).
Regarding claim 6, Pinos further discloses the electronic device defined in claim 4, wherein the additional conductive layer 116 is not overlapped by any portion of the second semiconductor layer (layer between 112 and 110).
Regarding claim 7, Pinos further discloses the electronic device defined in claim 4, wherein the additional conductive layer 116 is formed in a ring around a periphery of the array of light-emitting diodes (Fig. 3).
Regarding claim 9, Pinos further discloses the electronic device defined in claim 4, wherein each light-emitting diode in the array of light-emitting diodes further comprises: a multi-quantum wells layer 110 (Para. 73) that is interposed between the second semiconductor layer for that light-emitting diode and the common cathode 102.
Regarding claim 10, Pinos further discloses the electronic device defined in claim 9, wherein the array of light-emitting diodes further comprises: a substrate (Para. 72), wherein the first semiconductor layer 102 is interposed between the substrate and the additional conductive layer 106.
Claim(s) 11-12 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Pinos et al ((US 2023/0069410 A1) in view of Tsai et al (US 2010/0072487 A1) and further in view of Chou et al (US 2005/0007000 A1).
Regarding claim 11, Pinos in view of Tsai does not explicitly disclose the electronic device defined in claim 10, wherein the array of light-emitting diodes further comprises: a diffuser, wherein the substrate is interposed between the diffuser and the first semiconductor layer.
However, Chou discloses the array of light-emitting diodes further comprises: a diffuser 330 (Fig. 3a, Para. 30), wherein the substrate 320 is interposed between the diffuser 330 and the first semiconductor layer 316 (Para. 29).
Chou teaches the above modification is used to improve brightness of the device (Abstract). It would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to combine Pinos in view of Tsai structure with Chou diffuser as suggested above to improve brightness of the device (Abstract).
Regarding claim 12, Chou further discloses the electronic device defined in claim 9, wherein the array of light-emitting diodes further comprises: a diffuser 340 (Fig. 3B, Para. 31), wherein the first semiconductor layer 316 is interposed between the diffuser 340 and the additional conductive layer (obvious with Pinos reference).
Regarding claim 15, Tsai further discloses the electronic device defined in claim 1, wherein the plurality of conductive vias includes at least four conductive vias 180.
Allowable Subject Matter
Claims 8, 13 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 16-19 are allowed.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BILKIS JAHAN whose telephone number is (571)270-5022. The examiner can normally be reached Monday-Friday, 8:00 am-5 Pm.
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BILKIS . JAHAN
Primary Examiner
Art Unit 2817
/BILKIS JAHAN/Primary Examiner, Art Unit 2817
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