Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species I, reading on claims 1, 2, 6, 7, 9-13, 15-17, 19 and 20 in the reply filed on 04/17/2026 is acknowledged. Claim 18 has been canceled.
Claims 3-5, 8, 14 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 04/17/2026.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wada et al. (US 20210082921 A1; hereinafter “Wada”) (Wada has been listed in the 03/08/2023 IDS).
In re claim 1, Wada discloses in figs. 1-3, a semiconductor device comprising:
a first insulating layer 25 and a second insulating layer 23 arranged in a first direction Z (¶82);
a first conductive layer 14 disposed between the first insulating layer and the second insulating layer (¶82);
an oxide semiconductor layer 13 extending in the first direction Z, the oxide semiconductor layer 13 being opposed to the first insulating layer 25, the second insulating layer 23, and the first conductive layer 14 in a second direction Y intersecting with the first direction Z (¶37-38); and
a third insulating layer 15 disposed between the first insulating layer 25 and the oxide semiconductor layer 13, between the second insulating layer 23 and the oxide semiconductor layer 13, and between the first conductive layer 14 and the oxide semiconductor layer 13 (¶33),
wherein the third insulating layer 15 includes:
a first part (e.g., an upper portion of 15; hereinafter “P11”) that covers at least a part of a side surface in the second direction Y of the first insulating layer 25; and
a second part (e.g., a lower portion of 15; hereinafter “P12”) that covers at least a part of side surfaces in the second direction Y of the second insulating layer 23 and the first conductive layer 14, and
a first region 17 extending in a direction Y different from an extending direction Z of the first part P11 and an extending direction of the second part P12 is disposed between a region corresponding to the first part P11 and a region corresponding to the second part P12, and is in contact with the third insulating layer 15 and the oxide semiconductor layer 13 (¶33).
In re claim 2, Wada discloses in figs. 1-3, the semiconductor device according to claim 1, wherein the oxide semiconductor layer 13 includes:
a first semiconductor region (e.g., an upper portion of the OS layer 13 adjacent to insulating layer 25 and oxide layer 17; hereinafter “OS1”) having an outer peripheral surface surrounded by the first part of the third insulating layer P11; and
a second semiconductor region (e.g., the remaining portion of the OS layer 13 adjacent to insulating layers 24, 23, conductor 14 and drain electrode 12; hereinafter “OS2”) having an outer peripheral surface surrounded by the second part of the third insulating layer P12, and
when a width in the second direction Y of an end portion of the first semiconductor region (e.g., an end portion of OS1 adjacent to oxide layer 17) is assumed to be a first width (e.g., W1), the end portion of the first semiconductor region (i.e., the end portion of OS1 adjacent to oxide layer 17) being in contact with the second semiconductor region OS2; and
when a width in the second direction Y of an end portion of the second semiconductor region (e.g., portion of OS layer 13 adjacent to electrode 24) is assumed to be a second width (e.g., W2), the end portion of the second semiconductor region OS2 being in contact with the first semiconductor region,
the first width W1 is smaller than the second width W2.
In re claim 11, Wada discloses in figs. 1-3, the semiconductor device according to claim 1, comprising a second conductive layer 12 connected to one end portion in the first direction Z of the oxide semiconductor layer 13, wherein the second conductive layer 12 contains indium (In) and tin (Sn) (¶34).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6-7, 9-10, 12-13, 15-17, 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wada as applied to claim 1 above, and further in view of Colinge et al. (US 20140225184 A1; hereinafter “Colinge”).
In re claim 6, Wada discloses in figs. 1-3, the semiconductor device according to claim 1 outlined above.
Wada does not expressly disclose the device comprising a fourth insulating layer disposed between the first insulating layer and the third insulating layer,
the fourth insulating layer having at least one of a material different from a material of the first insulating layer or a film density different from a film density of the first insulating layer.
In the same field of endeavor, Colinge discloses in figs. 2A-2G, a semiconductor device comprising a fourth insulating layer 42 disposed between an first insulating layer 40 and a third insulating layer 38 (¶22),
the fourth insulating layer 42 having at least one of a material different from a material of the first insulating layer 40 (¶21, 28; Non-permeable layer 42 is formed of silicon nitride and dielectric layer 40 comprises silicon oxide (SiO.sub.2),) or a film density different from a film density of the first insulating layer.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to form a fourth insulating layer disposed between the first insulating layer and the third insulating layer in Wada to prevent oxygen from penetrating during local oxidation and hence protect the channel layer (¶23 of Colinge).
In re claim 7, Wada as modified by Colinge discloses the semiconductor device according to claim 6.
Wada further discloses in fig. 1-3, wherein an opposed surface of the first insulating layer (Wada: layer 25) to the oxide semiconductor layer 13 is not in contact with the third insulating layer 15.
In re claim 9, Wada as modified by Colinge discloses the semiconductor device according to claim 6.
Wada further discloses in fig. 1-3, wherein the second insulating layer 23 and the first conductive layer 14 are in contact with the third insulating layer 15.
In re claim 10, Wada as modified by Colinge discloses the semiconductor device according to claim 6, wherein the fourth insulating layer (Colinge: layer 42 in fig. 2G) surrounds an outer peripheral surface of the third insulating layer (Wada: 15 in fig. 3) in a first cross-sectional surface (X-Y surface) that extends in the second direction Y and a third direction X intersecting with the first direction Z and the second direction Y and includes the first insulating layer (Wada: 25 in fig. 3).
In re claim 12, Wada discloses in figs. 1-3, a semiconductor device comprising:
a first insulating layer 25 and a second insulating layer 23 arranged in a first direction Z (¶82);
a first conductive layer 14 disposed between the first insulating layer and the second insulating layer (¶82);
an oxide semiconductor layer 13 extending in the first direction Z, the oxide semiconductor layer 13 being opposed to the first insulating layer 25, the second insulating layer 23, and the first conductive layer 14 in a second direction Y intersecting with the first direction Z (¶37-38); and
a third insulating layer 15 disposed between the first insulating layer 25 and the oxide semiconductor layer 13, between the second insulating layer 23 and the oxide semiconductor layer 13, and between the first conductive layer 14 and the oxide semiconductor layer 13 (¶33).
Wada does not expressly disclose the device comprising a fourth insulating layer disposed between the first insulating layer and the third insulating layer,
the fourth insulating layer having at least one of a material different from a material of the first insulating layer or a film density different from a film density of the first insulating layer.
In the same field of endeavor, Colinge discloses in figs. 2A-2G, a semiconductor device comprising a fourth insulating layer 42 disposed between an first insulating layer 40 and a third insulating layer 38 (¶22),
the fourth insulating layer 42 having at least one of a material different from a material of the first insulating layer 40 (¶21, 28; Non-permeable layer 42 is formed of silicon nitride and dielectric layer 40 comprises silicon oxide (SiO.sub.2),) or a film density different from a film density of the first insulating layer.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to form a fourth insulating layer disposed between the first insulating layer and the third insulating layer in Wada to prevent oxygen from penetrating during local oxidation and hence protect the channel layer (¶23 of Colinge).
In re claim 13, Wada as modified by Colinge discloses the semiconductor device according to claim 12.
Wada further discloses in fig. 1-3, wherein an opposed surface of the first insulating layer (Wada: layer 25) to the oxide semiconductor layer 13 is not in contact with the third insulating layer 15.
In re claim 15, Wada as modified by Colinge discloses the semiconductor device according to claim 12.
Wada further discloses in fig. 1-3, wherein the second insulating layer 23 and the first conductive layer 14 are in contact with the third insulating layer 15.
In re claim 16, Wada as modified by Colinge discloses the semiconductor device according to claim 12.
Regarding the claim limitation “wherein the first insulating layer and the fourth insulating layer contain silicon (Si) and oxygen (O), and the film density of the first insulating layer differs from the film density of the fourth insulating layer” becomes optional, because claim 12 recites two alternate limitations for materials of the first insulating layer and the fourth insulating layer can be different. For example, either the fourth insulating layer having at least one of a material different from a material of the first insulating layer or a film density different from a film density of the first insulating layer. Because Wada as modified by Colinge discloses the fourth insulating layer having at least one of a material different from a material of the first insulating layer, the further narrow limitation of the alternative limitation becomes optional.
In re claim 17, Wada as modified by Colinge discloses the semiconductor device according to claim 12.
Wada further discloses in figs. 1-3, the semiconductor device according to claim 12, wherein the oxide semiconductor layer 13 includes:
a first semiconductor region (e.g., an upper portion of the OS layer 13 adjacent to insulating layer 25 and oxide layer 17; hereinafter “OS1”) having an outer peripheral surface surrounded by the first part of the third insulating layer P11; and
a second semiconductor region (e.g., the remaining portion of the OS layer 13 adjacent to insulating layers 24, 23, conductor 14 and drain electrode 12; hereinafter “OS2”) having an outer peripheral surface surrounded by the second part of the third insulating layer P12, and
when a width in the second direction Y of an end portion of the first semiconductor region (e.g., an end portion of OS1 adjacent to oxide layer 17) is assumed to be a first width (e.g., W1), the end portion of the first semiconductor region (i.e., the end portion of OS1 adjacent to oxide layer 17) being in contact with the second semiconductor region OS2; and
when a width in the second direction Y of an end portion of the second semiconductor region (e.g., portion of OS layer 13 adjacent to electrode 24) is assumed to be a second width (e.g., W2), the end portion of the second semiconductor region OS2 being in contact with the first semiconductor region,
the first width W1 is smaller than the second width W2.
In re claim 19, Wada as modified by Colinge discloses the semiconductor device according to claim 12, wherein the fourth insulating layer (Colinge: layer 42 in fig. 2G) surrounds an outer peripheral surface of the third insulating layer (Wada: 15 in fig. 3) in a first cross-sectional surface (X-Y surface) that extends in the second direction Y and a third direction X intersecting with the first direction Z and the second direction Y and includes the first insulating layer (Wada: 25 in fig. 3).
In re claim 20, Wada as modified by Colinge discloses the semiconductor device according to claim 12.
Wada further discloses in figs. 1-3, the semiconductor device according to claim 12, comprising a second conductive layer 12 connected to one end portion in the first direction Z of the oxide semiconductor layer 13, wherein the second conductive layer 12 contains indium (In) and tin (Sn) (¶34).
Conclusion
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/NILUFA RAHIM/Primary Examiner, Art Unit 2893
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