DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/18/2025 and 02/12/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the first active layer and the second active layer" in lines 5-6. There is insufficient antecedent basis for this limitation in the claim.
Claim 1 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Lines 4-5 "the gate contacts being laterally offset" is not mentioned in the specification.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6 are rejected under 35 U.S.C. 102 as being anticipated by Or-Bach et al. ( US 2017/0053906 A1; hereinafter Or-Bach)
Regarding claim 1, Or-Bach teaches an integrated circuit ( Fig. 10A ) comprising: a first array of memory bit arranged as a plurality of rows and a plurality of columns cells ( Fig.10A NPN array ); wherein a first memory bit cell of the first array comprises a gate contact ( Fig. 10A row with select gate channel #1020 ), between a first gate ( Fig. 10A #1020) of a first transistor ( Fig. 10A #1010 N, #1012 P, #1014 N ) and a second gate ( Fig. 10A: annotated version #1021 ) of a second transistor ( Fig. 10A middle row NPN region) , the gate contact ( Fig 10A #1020 ) being laterally offset ( Fig. 10A shows the gate contact has connections offset to the side of the active layers) relative to the first active layer ( Fig. 10A #1010N ) and the second active layer ( Fig. 10A: N region of middle row ) such that the gate contact overlaps only one active layer of a first active layer of the first transistor ( Fig. 10A #1010 N) and a second active layer of the second transistor ( Fig. 10A: N region of middle row).
Regarding claim 2, Or-Bach teaches the integrated circuit as recited in claim 1 ( as discussed above), wherein: each of the first transistor ( Fig. 10A #1020 ) and the second transistor ( Fig. 10A #1021 ) is a vertical gate all around (GAA) device ( Fig. 16B has the same configuration as Fig. 10A ; [0170] The process could include a step of isotropic etch to open the interlayer oxide #1616 so the following step of get forming could fill the gate all around the P regions) utilizing a plurality of nanosheets as a channel ( [ 0202] The thickness of these layers could be think as few nm to hundreds of nm ); and wherein in response to receiving an indication of a first read operation targeting a row of the plurality of rows comprising the first memory bit cell ( [0072] so that by selecting a specific bit-line and specific word-line one may select a specific memory cell to write to or read from ), the first array is configured to convey data stored in the first memory bit cell ( [0016] a device comprising: a first structure comprising first memory cells, said first memory cells comprising first transistors).
Regarding claim 3, Or-Bach teaches the integrated circuit as recited in claim 2 ( as discussed above), wherein: the second active layer ( Fig. 10A: N region of middle row) comprises a channel ( Fig. 10A #1021 ) configured to conduct current in a direction orthogonal to a direction of current flow in a channel of the first active layer ( Fig. 10C holding current from the pillars #1040); the first active layer ( Fig. 10A #1010N ) and the second active layer ( Fig. 10A: N region of middle row) do not overlap one another ( as shown in Fig. 10A ); and a distance between the first active layer and the second active layer is at least a width of a source or drain contact ( as shown in Fig. 10A).
Regarding claim 4, Or-Bach teaches the integrated circuit as recited in claim 3 ( as discussed above), wherein: the first memory bit cell ( [0072] so that by selecting a specific bit-line and specific word-line one may select a specific memory cell to write to or read from ) comprises a drain contact ( Fig. 4C transistor drains #422) contacting an area of a local interconnect layer of the second transistor ( Fig. 4C bit-lines #410 ), between drain nodes ( Fig. 4C #422) of the first transistor ( Fig. 10A #1010 N, #1012 P, #1014 N ) and the second transistor ( Fig. 10A: N P N region of middle row ); and the area of the local interconnect layer ( Fig. 10A #1010 N ) is not physically adjacent to the second active layer ( Fig. 10A: middle row layer equivalent to #1010N) of the second transistor ( [0098] Other options exist for the formation of such memory control lines grid, allowing selecting an individual transistor-memory cell by selecting its source, gate and drain defining a specific x,y,z location).
Regarding claim 5, Or-Bach teaches the integrated circuit as recited in claim 3 ( as discussed above), wherein the first memory bit cell ( Fig. 10A first row ) comprises an asymmetrical layout with respect to placement of transistors and signal nodes within the first memory bit cell ( Fig. 10A transistors are asymmetric to the control line ).
Regarding claim 6, Or-Bach teaches the integrated circuit as recited in claim 3 ( as discussed above), further comprising a second array of memory bit cells ( Fig. 11A #1120 ) comprising a plurality of rows and a plurality of columns ( Fig. 11A #1122 ), wherein a highest metal layer used for signal routing in a second memory bit cell ( Fig. 11A #1124 ) of the second array ( Fig. 11A #1120 ) is a metal zero layer ( [0072] These memory control lines could therefore be comprising semiconductor materials such as silicon or conductive metal layers such as tungsten aluminum or copper ).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 7 is rejected under U.S.C. 103 as being unpatentable over Or-Bach et al.; US 2017/0053906 A1; 08/2016 in view of Hwang et al.; US 2024/0414912 A1; 07/2021
Claim 7: Or-Bach discloses the integrated circuit as recited in claim 6 ( as discussed above).
Or-Bach does not appear to disclose a height of the first memory bit cell is less than a height of the second memory bit cell; and a width of the first memory bit cell is greater than a width of the second memory bit cell.
However, Hwang teaches a height of the first memory bit cell ( Fig. 1 #262 far left is connected to first cell interconnection line #272 ) is less than a height of the second memory bit cell (Fig. 1 #262 next column over from far left is greater height ) ; and a width of the first memory bit cell is greater than a width of the second memory bit cell ( [0051] the first second and third cell contact plugs #262, #264, and #266 may have lateral surfaces in which widths of the first, second, and third cell contact plugs #262, #264, and #266 decrease toward the second substrate #201).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Hwang with Or-Bach to implement a height of the first memory bit cell is less than a height of the second memory bit cell; and a width of the first memory bit cell is greater than a width of the second memory bit cell because cells designed for high-speed operation may have narrower, more direct signal paths.
Response to Amendment / Arguments
The amendment filed 02/10/26 is objected to under 35 U.S.C. 132(a) because it introduces new matter into the disclosure. 35 U.S.C. 132(a) states that no amendment shall introduce new matter into the disclosure of the invention. The added material which is not supported by the original disclosure is as follows: "the gate contact being laterally offset" .
Applicant is required to cancel the new matter in the reply to this Office Action.
Applicant's arguments filed 02/12/2026 have been fully considered but they are not persuasive. The amendments to claim 1 are rejected under 35 USC 112 as lacking an antecedent basis and not being supported by the specification.
Applicant’s arguments filed 02/12/2026 have been fully considered but they are not persuasive. The restriction of 06/12/2025 is maintained since the amendment to claim 15 includes a computing system that executes instructions using source data as discussed in the restriction between Inventions II and III as well as the restriction between Inventions I and III.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIMBERLY N FREY whose telephone number is (571)272-5068. The examiner can normally be reached Monday - Friday 7:30 am - 5 pm.
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/K.N.F./ Examiner, Art Unit 2817
/MARLON T FLETCHER/ Supervisory Primary Examiner, Art Unit 2817