DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/03/2026 has been entered.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/15/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 are rejected under U.S.C. 103 as being unpatentable over Or-Bach et al.; US 2017/0053906 A1; 08/2016 in view of Wang et al.; US 2025/0151543 A1; 09/2022 and Jung et al.; US 2002/0053706 A1; 07/2001
Claim 1: Or-Bach discloses an integrated circuit ( Fig. 10A ) comprising: a first array of memory bit arranged as a plurality of rows and a plurality of columns cells ( Fig.10A NPN array ); wherein a first memory bit cell of the first array comprises:
Or-Bach does not appear to disclose a first transistor comprising a first active layer and a first gate; a second transistor comprising a second active layer and a second gate; and a gate contact , electrically connected to the first gate and the second gate; wherein the first gate and the second gate form a T-shape with respect to one another, the gate contact overlaps only one of the first active layer and the second active layer, and the first active layer and the second active layer do not overlap one another
Wang discloses a first transistor ( Fig. 25 first transistor 20 ) comprising a first active layer ( Fig. 25 first active layer 21 ) and a first gate ( Fig. 25 first gate electrode 22 ); a second transistor ( Fig. 25 second transistor 30 ) comprising a second active layer ( Fig. 25 second active layer 31 ) and a second gate ( Fig. 25 second gate electrode 32 ) ; and a gate contact ( [0072] In an exemplary implementation mode, a gate electrode of the first transistor T1 is connected with the second scan signal line S2 ), electrically connected to the first gate ( as discussed above ) and the second gate ( [0073] In an exemplary implementation mode, a gate electrode of the second transistor T2 is connected with the first scan signal line S1 ).
Wang does not appear to disclose the first gate and the second gate form a T-shape with respect to one another, the gate contact overlaps only one of the first active layer and the second active layer, and the first active layer and the second active layer do not overlap one another.
However, Jung teaches the first gate ( Fig. 4A first gate contact region 230 ) and the second gate ( Fig. 4A second gate contact region 280 ) form a T-shape ( Fig. 4A T-shape gate interconnect 212 ) with respect to one another, the gate contact overlaps only one of the first active layer ( Fig. 4A two first source/drain regions 222 ) and the second active layer ( Fig. 4A two second source/drain regions 272 ) , and the first active layer and the second active layer do not overlap one another ( as shown in Fig. 4A )
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Jung with Or-Bach, and Wang to implement a first transistor comprising a first active layer and a first gate; a second transistor comprising a second active layer and a second gate; and a gate contact , electrically connected to the first gate and the second gate; wherein the first gate and the second gate form a T-shape with respect to one another, the gate contact overlaps only one of the first active layer and the second active layer, and the first active layer and the second active layer do not overlap one another because this approach enables cross coupling or local interconnects between transistors.
Claim 2: Or-Bach, Wang, and Jung disclose the integrated circuit as recited in claim 1 ( as discussed above).
Or-Bach teaches each of the first transistor ( Fig. 10A #1020 ) and the second transistor ( Fig. 10A #1021 ) is a vertical gate all around (GAA) device ( Fig. 16B has the same configuration as Fig. 10A ; [0170] The process could include a step of isotropic etch to open the interlayer oxide #1616 so the following step of get forming could fill the gate all around the P regions) utilizing a plurality of nanosheets as a channel ( [ 0202] The thickness of these layers could be think as few nm to hundreds of nm ); and wherein in response to receiving an indication of a first read operation targeting a row of the plurality of rows comprising the first memory bit cell ( [0072] so that by selecting a specific bit-line and specific word-line one may select a specific memory cell to write to or read from ), the first array is configured to convey data stored in the first memory bit cell ( [0016] a device comprising: a first structure comprising first memory cells, said first memory cells comprising first transistors).
Claim 3: Or-Bach, Wang, and Jung disclose the integrated circuit as recited in claim 2 ( as discussed above).
Or-Bach teaches the second active layer ( Fig. 10A: N region of middle row) comprises a channel ( Fig. 10A #1021 ) configured to conduct current in a direction orthogonal to a direction of current flow in a channel of the first active layer ( Fig. 10C holding current from the pillars #1040); a distance between the first active layer and the second active layer is at least a width of a source or drain contact ( as shown in Fig. 10A).
Claim 4: Or-Bach, Wang, and Jung disclose the integrated circuit as recited in claim 3 ( as discussed above).
Or-Bach teaches the first memory bit cell ( [0072] so that by selecting a specific bit-line and specific word-line one may select a specific memory cell to write to or read from ) comprises a drain contact ( Fig. 4C transistor drains #422) contacting an area of a local interconnect layer of the second transistor ( Fig. 4C bit-lines #410 ), between drain nodes ( Fig. 4C #422) of the first transistor ( Fig. 10A #1010 N, #1012 P, #1014 N ) and the second transistor ( Fig. 10A: N P N region of middle row ); and the area of the local interconnect layer ( Fig. 10A #1010 N ) is not physically adjacent to the second active layer ( Fig. 10A: middle row layer equivalent to #1010N) of the second transistor ( [0098] Other options exist for the formation of such memory control lines grid, allowing selecting an individual transistor-memory cell by selecting its source, gate and drain defining a specific x,y,z location).
Claim 5: Or-Bach, Wang, and Jung disclose the integrated circuit as recited in claim 3 ( as discussed above).
Or-Bach teaches the first memory bit cell ( Fig. 10A first row ) comprises an asymmetrical layout with respect to placement of transistors and signal nodes within the first memory bit cell ( Fig. 10A transistors are asymmetric to the control line ).
Claim 6: Or-Bach, Wang, and Jung disclose the integrated circuit as recited in claim 3 ( as discussed above).
Or-Bach teaches a second array of memory bit cells ( Fig. 11A #1120 ) comprising a plurality of rows and a plurality of columns ( Fig. 11A #1122 ), wherein a highest metal layer used for signal routing in a second memory bit cell ( Fig. 11A #1124 ) of the second array ( Fig. 11A #1120 ) is a metal zero layer ( [0072] These memory control lines could therefore be comprising semiconductor materials such as silicon or conductive metal layers such as tungsten aluminum or copper ).
Claim 7 is rejected under U.S.C. 103 as being unpatentable over Or-Bach et al.; US 2017/0053906 A1; 08/2016 in view of Wang et al.; US 2025/0151543 A1; 09/2022 and Jung et al.; US 2002/0053706 A1; 07/2001 as it relates to claim 6 above and further in view of Hwang et al.; US 2024/0414912 A1; 07/2021
Claim 7: Or-Bach, Wang, and Jung discloses the integrated circuit as recited in claim 6 ( as discussed above).
Neither Or-Bach nor Wang nor Jung appear to disclose a height of the first memory bit cell is less than a height of the second memory bit cell; and a width of the first memory bit cell is greater than a width of the second memory bit cell.
However, Hwang teaches a height of the first memory bit cell ( Fig. 1 #262 far left is connected to first cell interconnection line #272 ) is less than a height of the second memory bit cell (Fig. 1 #262 next column over from far left is greater height ) ; and a width of the first memory bit cell is greater than a width of the second memory bit cell ( [0051] the first second and third cell contact plugs #262, #264, and #266 may have lateral surfaces in which widths of the first, second, and third cell contact plugs #262, #264, and #266 decrease toward the second substrate #201).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Hwang with Or-Bach, Wang, and Jung to implement a height of the first memory bit cell is less than a height of the second memory bit cell; and a width of the first memory bit cell is greater than a width of the second memory bit cell because cells designed for high-speed operation may have narrower, more direct signal paths.
Response to Amendment / Arguments
Applicant’s arguments, see pages 7-8 of the remarks, filed 06/03/2026, with respect to the 112 rejections of claim 1 have been fully considered and are persuasive. The rejection of 03/17/2026 has been withdrawn.
Applicant’s arguments, see pages 8-9 of the remarks, filed 06/03/2026, with respect to the rejection of claim 1 under 35 U.S.C. 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Wang and Jung.
Applicant's arguments, see page 9 of the remarks, filed 06/03/2026 with respect to the restriction on claim 15 have been fully considered but they are not persuasive. Applicant argues that the computing system should be part of the elected group. Applicant argues that the claim does not mention executing instructions using source data. However, the amended claim 15 is a distinct combination of the subcombination described in claims 1-7. This is due to the fact that the subcombination has a separate utility such as an internet of things application. Additionally, the combination does not require the particulars of the subcombination as claimed to execute instructions.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIMBERLY N FREY whose telephone number is (571)272-5068. The examiner can normally be reached Monday - Friday 7:30 am - 5 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at (571)272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/K.N.F./Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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